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Commit 240b1c6e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'arm-soc/for-4.6/devicetree' of http://github.com/Broadcom/stblinux into next/dt 

Merge "Broadcom devicetree changes for 4.6" from Florian Fainelli:

This pull request contains Broadcom ARM-based SoCs Device Tree changes:

- Rafal adds a Device Tree for the D-Link DIR-885L router which is based on the
  BCM47094 SoC similar to the BCM4709

- Simran adds proper audio clock Device Tree nodes to the Cygnus platforms

- Martin adds the auxiliary SPI controllers, makes the UART naming convention
  more standard, and finally adds the auxiliary UART found in the BCM2835 to the
  BCM2835 Device Tree

- Remi adds PWM clock support to the BCM2835 Device Tree

- Lubomir adds a Device Tree for the Raspberry Pi Model A

- Alexander adds Device Tree information for the Raspberry Pi USB power domain

- Dhananjay enables the GPIO-A controller for the Northstar Plus SoCs

- Jon fixes the PCIE Device Tree nodes by pulling them out of the bus-level node,
  removes duplicate CPU definitions, adds PMU nodes, SP804 timers, and SP805 watchdog
  to the Northstar Plus SoCs

* tag 'arm-soc/for-4.6/devicetree' of http://github.com/Broadcom/stblinux:
  ARM: bcm2835: add bcm2835-aux-uart support to DT
  ARM: dts: NSP: Add SP805 Support to DT
  ARM: dts: NSP: Add SP804 Support to DT
  ARM: dts: NSP: Add PMU Support to DT
  ARM: dts: NSP: Fix CPU DT issue
  ARM: dts: NSP: Fix PCIE DT issue
  ARM: dts: enable GPIO-a for Broadcom NSP
  ARM: bcm2835: Add the Raspberry Pi power domain driver to the DT.
  ARM: bcm2835: dt: Add Raspberry Pi Model A
  ARM: bcm2835: follow dt uart node-naming convention
  ARM: bcm2835: Add PWM clock support to the device tree
  ARM: bcm2835: add the auxiliary spi1 and spi2 to the device tree
  ARM: dts: Add audio clock to the existing Broadcom Cygnus clock DT
  ARM: BCM5301X: Add DT for D-Link DIR-885L
parents ac037ee0 ac07c41c

arch/arm/boot/dts/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_AXXIA) += \ 
	axm5516-amarillo.dtb

dtb-$(CONFIG_ARCH_BCM2835) += \

	bcm2835-rpi-b.dtb \

	bcm2835-rpi-a.dtb \

	bcm2835-rpi-b-rev2.dtb \

	bcm2835-rpi-b-plus.dtb \

	bcm2835-rpi-a-plus.dtb \
@@ -81,6 +82,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ 
	bcm4709-buffalo-wxr-1900dhp.dtb \

	bcm4709-netgear-r7000.dtb \

	bcm4709-netgear-r8000.dtb \

	bcm47094-dlink-dir-885l.dtb \

	bcm94708.dtb \

	bcm94709.dtb \

	bcm953012k.dtb

arch/arm/boot/dts/bcm-cygnus-clock.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -121,4 +121,13 @@ clocks { 
		clocks = <&osc>;

		clock-output-names = "keypad", "adc/touch", "pwm";

	};



	audiopll: audiopll {

		#clock-cells = <1>;

		compatible = "brcm,cygnus-audiopll";

		reg = <0x180aeb00 0x68>;

		clocks = <&osc>;

		clock-output-names = "audiopll", "ch0_audio",

					"ch1_audio", "ch2_audio";

	};

};

arch/arm/boot/dts/bcm-nsp.dtsi

+119 −86
Original line number Diff line number Diff line
@@ -45,14 +45,14 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x0>;

		};



		cpu@1 {

		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;
@@ -62,24 +62,19 @@ 
		};

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0>, <&cpu1>;

	};



	mpcore {

		compatible = "simple-bus";

		ranges = <0x00000000 0x19000000 0x00023000>;

		#address-cells = <1>;

		#size-cells = <1>;



		cpus {

			#address-cells = <1>;

			#size-cells = <0>;



			cpu@0 {

				device_type = "cpu";

				compatible = "arm,cortex-a9";

				next-level-cache = <&L2>;

				reg = <0x0>;

			};

		};



		a9pll: arm_clk@00000 {

			#clock-cells = <0>;

			compatible = "brcm,nsp-armpll";
@@ -169,6 +164,18 @@ 
		#address-cells = <1>;

		#size-cells = <1>;



		gpioa: gpio@0020 {

			compatible = "brcm,nsp-gpio-a";

			reg = <0x0020 0x70>,

			      <0x3f1c4 0x1c>;

			#gpio-cells = <2>;

			gpio-controller;

			ngpios = <32>;

			interrupt-controller;

			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

			gpio-ranges = <&pinctrl 0 0 32>;

		};



		uart0: serial@0300 {

			compatible = "ns16550a";

			reg = <0x0300 0x100>;
@@ -185,9 +192,85 @@ 
			status = "disabled";

		};



		pcie0: pcie@12000 {

		nand: nand@26000 {

			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";

			reg = <0x026000 0x600>,

			      <0x11b408 0x600>,

			      <0x026f00 0x20>;

			reg-names = "nand", "iproc-idm", "iproc-ext";

			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;



			#address-cells = <1>;

			#size-cells = <0>;



			brcm,nand-has-wp;

		};



		ccbtimer0: timer@34000 {

			compatible = "arm,sp804";

			reg = <0x34000 0x1000>;

			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&iprocslow>;

			clock-names = "apb_pclk";

		};



		ccbtimer1: timer@35000 {

			compatible = "arm,sp804";

			reg = <0x35000 0x1000>;

			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&iprocslow>;

			clock-names = "apb_pclk";

		};



		i2c0: i2c@38000 {

			compatible = "brcm,iproc-i2c";

			reg = <0x38000 0x50>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;

			clock-frequency = <100000>;

		};



		watchdog@39000 {

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x39000 0x1000>;

			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&iprocslow>, <&iprocslow>;

			clock-names = "wdogclk", "apb_pclk";

		};



		lcpll0: lcpll0@3f100 {

			#clock-cells = <1>;

			compatible = "brcm,nsp-lcpll0";

			reg = <0x3f100 0x14>;

			clocks = <&osc>;

			clock-output-names = "lcpll0", "pcie_phy", "sdio",

					     "ddr_phy";

		};



		genpll: genpll@3f140 {

			#clock-cells = <1>;

			compatible = "brcm,nsp-genpll";

			reg = <0x3f140 0x24>;

			clocks = <&osc>;

			clock-output-names = "genpll", "phy", "ethernetclk",

					     "usbclk", "iprocfast", "sata1",

					     "sata2";

		};



		pinctrl: pinctrl@3f1c0 {

			compatible = "brcm,nsp-pinmux";

			reg = <0x3f1c0 0x04>,

			      <0x30028 0x04>,

			      <0x3f408 0x04>;

		};

	};



	pcie0: pcie@18012000 {

		compatible = "brcm,iproc-pcie";

			reg = <0x12000 0x1000>;

		reg = <0x18012000 0x1000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;
@@ -209,9 +292,9 @@ 
		status = "disabled";

	};



		pcie1: pcie@13000 {

	pcie1: pcie@18013000 {

		compatible = "brcm,iproc-pcie";

			reg = <0x13000 0x1000>;

		reg = <0x18013000 0x1000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;
@@ -233,9 +316,9 @@ 
		status = "disabled";

	};



		pcie2: pcie@14000 {

	pcie2: pcie@18014000 {

		compatible = "brcm,iproc-pcie";

			reg = <0x14000 0x1000>;

		reg = <0x18014000 0x1000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;
@@ -256,54 +339,4 @@ 


		status = "disabled";

	};



		nand: nand@26000 {

			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";

			reg = <0x026000 0x600>,

			      <0x11b408 0x600>,

			      <0x026f00 0x20>;

			reg-names = "nand", "iproc-idm", "iproc-ext";

			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;



			#address-cells = <1>;

			#size-cells = <0>;



			brcm,nand-has-wp;

		};



		i2c0: i2c@38000 {

			compatible = "brcm,iproc-i2c";

			reg = <0x38000 0x50>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;

			clock-frequency = <100000>;

		};



		lcpll0: lcpll0@3f100 {

			#clock-cells = <1>;

			compatible = "brcm,nsp-lcpll0";

			reg = <0x3f100 0x14>;

			clocks = <&osc>;

			clock-output-names = "lcpll0", "pcie_phy", "sdio",

					     "ddr_phy";

		};



		genpll: genpll@3f140 {

			#clock-cells = <1>;

			compatible = "brcm,nsp-genpll";

			reg = <0x3f140 0x24>;

			clocks = <&osc>;

			clock-output-names = "genpll", "phy", "ethernetclk",

					     "usbclk", "iprocfast", "sata1",

					     "sata2";

		};



		pinctrl: pinctrl@3f1c0 {

			compatible = "brcm,nsp-pinmux";

			reg = <0x3f1c0 0x04>,

			      <0x30028 0x04>,

			      <0x3f408 0x04>;

		};

	};

};

arch/arm/boot/dts/bcm2835-rpi-a.dts

0 → 100644
+24 −0
Original line number Diff line number Diff line 
/dts-v1/;

#include "bcm2835.dtsi"

#include "bcm2835-rpi.dtsi"



/ {

	compatible = "raspberrypi,model-a", "brcm,bcm2835";

	model = "Raspberry Pi Model A";



	leds {

		act {

			gpios = <&gpio 16 1>;

		};

	};

};



&gpio {

	pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;



	/* I2S interface */

	i2s_alt2: i2s_alt2 {

		brcm,pins = <28 29 30 31>;

		brcm,function = <BCM2835_FSEL_ALT2>;

	};

};

arch/arm/boot/dts/bcm2835-rpi.dtsi

+16 −0
Original line number Diff line number Diff line 
#include <dt-bindings/power/raspberrypi-power.h>



/ {

	memory {

		reg = <0 0x10000000>;
@@ -18,6 +20,12 @@ 
			compatible = "raspberrypi,bcm2835-firmware";

			mboxes = <&mailbox>;

		};



		power: power {

			compatible = "raspberrypi,bcm2835-power";

			firmware = <&firmware>;

			#power-domain-cells = <1>;

		};

	};

};
@@ -58,3 +66,11 @@ 
	status = "okay";

	bus-width = <4>;

};



&pwm {

	status = "okay";

};



&usb {

	power-domains = <&power RPI_POWER_DOMAIN_USB>;

};