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Commit 224f611c authored by Michal Ludvig's avatar Michal Ludvig Committed by Linus Torvalds
Browse files

[PATCH] x86: VIA C7 CPU flags 



New CPU flags for next generation of crypto engine as found in VIA C7
processors.

Signed-off-by: default avatarMichal Ludvig <michal@logix.cz>
Cc: Andi Kleen <ak@muc.de>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 7e04a118

arch/i386/kernel/cpu/proc.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -52,7 +52,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) 




		/* VIA/Cyrix/Centaur-defined */

		/* VIA/Cyrix/Centaur-defined */

		NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",

		NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		"ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

include/asm-i386/cpufeature.h

+12 −0
Original line number Original line Diff line number Diff line
@@ -88,6 +88,12 @@ 
#define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* on-CPU RNG enabled */

#define X86_FEATURE_XSTORE_EN	(5*32+ 3) /* on-CPU RNG enabled */

#define X86_FEATURE_XCRYPT	(5*32+ 6) /* on-CPU crypto (xcrypt insn) */

#define X86_FEATURE_XCRYPT	(5*32+ 6) /* on-CPU crypto (xcrypt insn) */

#define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* on-CPU crypto enabled */

#define X86_FEATURE_XCRYPT_EN	(5*32+ 7) /* on-CPU crypto enabled */

#define X86_FEATURE_ACE2	(5*32+ 8) /* Advanced Cryptography Engine v2 */

#define X86_FEATURE_ACE2_EN	(5*32+ 9) /* ACE v2 enabled */

#define X86_FEATURE_PHE		(5*32+ 10) /* PadLock Hash Engine */

#define X86_FEATURE_PHE_EN	(5*32+ 11) /* PHE enabled */

#define X86_FEATURE_PMM		(5*32+ 12) /* PadLock Montgomery Multiplier */

#define X86_FEATURE_PMM_EN	(5*32+ 13) /* PMM enabled */





/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */

/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */

#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */

#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */
@@ -121,6 +127,12 @@ 
#define cpu_has_xstore_enabled	boot_cpu_has(X86_FEATURE_XSTORE_EN)

#define cpu_has_xstore_enabled	boot_cpu_has(X86_FEATURE_XSTORE_EN)

#define cpu_has_xcrypt		boot_cpu_has(X86_FEATURE_XCRYPT)

#define cpu_has_xcrypt		boot_cpu_has(X86_FEATURE_XCRYPT)

#define cpu_has_xcrypt_enabled	boot_cpu_has(X86_FEATURE_XCRYPT_EN)

#define cpu_has_xcrypt_enabled	boot_cpu_has(X86_FEATURE_XCRYPT_EN)

#define cpu_has_ace2		boot_cpu_has(X86_FEATURE_ACE2)

#define cpu_has_ace2_enabled	boot_cpu_has(X86_FEATURE_ACE2_EN)

#define cpu_has_phe		boot_cpu_has(X86_FEATURE_PHE)

#define cpu_has_phe_enabled	boot_cpu_has(X86_FEATURE_PHE_EN)

#define cpu_has_pmm		boot_cpu_has(X86_FEATURE_PMM)

#define cpu_has_pmm_enabled	boot_cpu_has(X86_FEATURE_PMM_EN)





#endif /* __ASM_I386_CPUFEATURE_H */

#endif /* __ASM_I386_CPUFEATURE_H */