Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 221ab43e authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: don't read or write GEN6_PMIIR on Gen 5 



The register doesn't exist on Gen 5.

v2: Simplify checks since pm_iir is always 0 on Gen 5 (Chris)

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9719fb98

drivers/gpu/drm/i915/i915_irq.c

+7 −5
Original line number Diff line number Diff line
@@ -1384,7 +1384,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) 
	struct drm_device *dev = (struct drm_device *) arg;

	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	int ret = IRQ_NONE;

	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;

	u32 de_iir, gt_iir, de_ier, pm_iir = 0, sde_ier;



	atomic_inc(&dev_priv->irq_received);
@@ -1404,9 +1404,10 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) 


	de_iir = I915_READ(DEIIR);

	gt_iir = I915_READ(GTIIR);

	if (IS_GEN6(dev))

		pm_iir = I915_READ(GEN6_PMIIR);



	if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))

	if (de_iir == 0 && gt_iir == 0 && pm_iir == 0)

		goto done;



	ret = IRQ_HANDLED;
@@ -1419,11 +1420,12 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) 
	if (de_iir)

		ilk_display_irq_handler(dev, de_iir);



	if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)

	if (pm_iir & GEN6_PM_RPS_EVENTS)

		gen6_rps_irq_handler(dev_priv, pm_iir);



	I915_WRITE(GTIIR, gt_iir);

	I915_WRITE(DEIIR, de_iir);

	if (pm_iir)

		I915_WRITE(GEN6_PMIIR, pm_iir);



done: