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Commit 21f18970 authored by Simon Horman's avatar Simon Horman
Browse files

ARM: dts: r7s72100: Remove unnecessary clock-output-names properties 



* Fixed rate and fixed factor clocks do not require an
  clock-output-names property.
* Since 07705583 ("clk: shmobile: div6: Make clock-output-names
  optional") Renesas div6 clocks do not require a clock-output-names
  property.

In the above cases there is only one clock output and its name is taken
from that of the clock node.  Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.

Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b19dd47b

arch/arm/boot/dts/r7s72100.dtsi

+5 −10
Original line number Diff line number Diff line
@@ -37,46 +37,41 @@ 
		#size-cells = <1>;



		/* External clocks */

		extal_clk: extal_clk {

		extal_clk: extal {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board */

			clock-frequency = <0>;

			clock-output-names = "extal";

		};



		usb_x1_clk: usb_x1_clk {

		usb_x1_clk: usb_x1 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board */

			clock-frequency = <0>;

			clock-output-names = "usb_x1";

		};



		/* Fixed factor clocks */

		b_clk: b_clk {

		b_clk: b {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <3>;

			clock-output-names = "b";

		};

		p1_clk: p1_clk {

		p1_clk: p1 {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <6>;

			clock-output-names = "p1";

		};

		p0_clk: p0_clk {

		p0_clk: p0 {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <12>;

			clock-output-names = "p0";

		};



		/* Special CPG clocks */