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Commit 21bffe57 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a7795: Correct parent clock of INTC-AP 



According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
September 8, 2017, the parent clock of the INTC-AP module clock on R-Car
H3 ES2.0 is S0D3.

This change has no functional impact.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b4021bbe

drivers/clk/renesas/r8a7795-cpg-mssr.c

+2 −1
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("usb-dmac1",		 331,	R8A7795_CLK_S3D1),

	DEF_MOD("rwdt",			 402,	R8A7795_CLK_R),

	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S3D1),

	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S0D3),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S0D3),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S0D3),

	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),
@@ -348,6 +348,7 @@ static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = { 
	{ MOD_CLK_ID(217), R8A7795_CLK_S3D1 },	/* SYS-DMAC2 */

	{ MOD_CLK_ID(218), R8A7795_CLK_S3D1 },	/* SYS-DMAC1 */

	{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 },	/* SYS-DMAC0 */

	{ MOD_CLK_ID(408), R8A7795_CLK_S3D1 },	/* INTC-AP */

	{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 },	/* AUDMAC1 */

	{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 },	/* AUDMAC0 */

	{ MOD_CLK_ID(523), R8A7795_CLK_S3D4 },	/* PWM */