Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 21a2c58a authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Record the RING_MODE register for post-mortem debugging 



Just another useful register to inspect following a GPU hang.

v2: Remove partial decoding of RING_MODE to userspace, be consistent and
use GEN > 2 guards around RING_MODE everywhere.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471254551-25805-32-git-send-email-chris@chris-wilson.co.uk
parent 57bc699d

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -757,6 +757,7 @@ struct drm_i915_error_state { 
		u32 tail;

		u32 tail;

		u32 head;

		u32 head;

		u32 ctl;

		u32 ctl;

		u32 mode;

		u32 hws;

		u32 hws;

		u32 ipeir;

		u32 ipeir;

		u32 ipehr;

		u32 ipehr;

drivers/gpu/drm/i915/i915_gpu_error.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -236,6 +236,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, 
	err_printf(m, "  HEAD:  0x%08x\n", ee->head);

	err_printf(m, "  HEAD:  0x%08x\n", ee->head);

	err_printf(m, "  TAIL:  0x%08x\n", ee->tail);

	err_printf(m, "  TAIL:  0x%08x\n", ee->tail);

	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);

	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);

	err_printf(m, "  MODE:  0x%08x\n", ee->mode);

	err_printf(m, "  HWS:   0x%08x\n", ee->hws);

	err_printf(m, "  HWS:   0x%08x\n", ee->hws);

	err_printf(m, "  ACTHD: 0x%08x %08x\n",

	err_printf(m, "  ACTHD: 0x%08x %08x\n",

		   (u32)(ee->acthd>>32), (u32)ee->acthd);

		   (u32)(ee->acthd>>32), (u32)ee->acthd);
@@ -1005,6 +1006,8 @@ static void error_record_engine_registers(struct drm_i915_error_state *error, 
	ee->head = I915_READ_HEAD(engine);

	ee->head = I915_READ_HEAD(engine);

	ee->tail = I915_READ_TAIL(engine);

	ee->tail = I915_READ_TAIL(engine);

	ee->ctl = I915_READ_CTL(engine);

	ee->ctl = I915_READ_CTL(engine);

	if (INTEL_GEN(dev_priv) > 2)

		ee->mode = I915_READ_MODE(engine);





	if (I915_NEED_GFX_HWS(dev_priv)) {

	if (I915_NEED_GFX_HWS(dev_priv)) {

		i915_reg_t mmio;

		i915_reg_t mmio;

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −3
Original line number Original line Diff line number Diff line
@@ -498,7 +498,7 @@ static bool stop_ring(struct intel_engine_cs *engine) 
{

{

	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *dev_priv = engine->i915;





	if (!IS_GEN2(dev_priv)) {

	if (INTEL_GEN(dev_priv) > 2) {

		I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));

		I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));

		if (intel_wait_for_register(dev_priv,

		if (intel_wait_for_register(dev_priv,

					    RING_MI_MODE(engine->mmio_base),

					    RING_MI_MODE(engine->mmio_base),
@@ -520,7 +520,7 @@ static bool stop_ring(struct intel_engine_cs *engine) 
	I915_WRITE_HEAD(engine, 0);

	I915_WRITE_HEAD(engine, 0);

	I915_WRITE_TAIL(engine, 0);

	I915_WRITE_TAIL(engine, 0);





	if (!IS_GEN2(dev_priv)) {

	if (INTEL_GEN(dev_priv) > 2) {

		(void)I915_READ_CTL(engine);

		(void)I915_READ_CTL(engine);

		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));

		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));

	}

	}
@@ -2142,7 +2142,8 @@ void intel_engine_cleanup(struct intel_engine_cs *engine) 
	dev_priv = engine->i915;

	dev_priv = engine->i915;





	if (engine->buffer) {

	if (engine->buffer) {

		WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);

		WARN_ON(INTEL_GEN(dev_priv) > 2 &&

			(I915_READ_MODE(engine) & MODE_IDLE) == 0);





		intel_ring_unpin(engine->buffer);

		intel_ring_unpin(engine->buffer);

		intel_ring_free(engine->buffer);

		intel_ring_free(engine->buffer);