Merge tag 'usb-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next

What:		/config/usb-gadget/gadget/functions/uac1.name

Date:		Sep 2014

KernelVersion:	3.18

Description:

		The attributes:

		audio_buf_size - audio buffer size

		fn_cap - capture pcm device file name

		fn_cntl - control device file name

		fn_play - playback pcm device file name

		req_buf_size - ISO OUT endpoint request buffer size

		req_count - ISO OUT endpoint request count

What:		/config/usb-gadget/gadget/functions/uac2.name

Date:		Sep 2014

KernelVersion:	3.18

Description:

		The attributes:

		c_chmask - capture channel mask

		c_srate - capture sampling rate

		c_ssize - capture sample size (bytes)

		p_chmask - playback channel mask

		p_srate - playback sampling rate

		p_ssize - playback sample size (bytes)

Qualcomm DWC3 HS AND SS PHY CONTROLLER

--------------------------------------

DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer

controllers.  Each DWC3 PHY controller should have its own node.

Required properties:

- compatible: should contain one of the following:

	- "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller

	- "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller

- reg: offset and length of the DWC3 PHY controller register set

- #phy-cells: must be zero

- clocks: a list of phandles and clock-specifier pairs, one for each entry in

  clock-names.

- clock-names: Should contain "ref" for the PHY reference clock

Optional clocks:

  "xo"		External reference clock

Example:

		phy@100f8800 {

			compatible = "qcom,dwc3-hs-usb-phy";

			reg = <0x100f8800 0x30>;

			clocks = <&gcc USB30_0_UTMI_CLK>;

			clock-names = "ref";

			#phy-cells = <0>;

			status = "ok";

		};

		phy@100f8830 {

			compatible = "qcom,dwc3-ss-usb-phy";

			reg = <0x100f8830 0x30>;

			clocks = <&gcc USB30_0_MASTER_CLK>;

			clock-names = "ref";

			#phy-cells = <0>;

			status = "ok";

		};

ST DWC3 glue logic

This file documents the parameters for the dwc3-st driver.

This driver controls the glue logic used to configure the dwc3 core on

STiH407 based platforms.

Required properties:

 - compatible	: must be "st,stih407-dwc3"

 - reg		: glue logic base address and USB syscfg ctrl register offset

 - reg-names	: should be "reg-glue" and "syscfg-reg"

 - st,syscon	: should be phandle to system configuration node which

		  encompasses the glue registers

 - resets	: list of phandle and reset specifier pairs. There should be two entries, one

		  for the powerdown and softreset lines of the usb3 IP

 - reset-names	: list of reset signal names. Names should be "powerdown" and "softreset"

See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt

See: Documentation/devicetree/bindings/reset/reset.txt

 - #address-cells, #size-cells : should be '1' if the device has sub-nodes

   with 'reg' property

 - pinctl-names	: A pinctrl state named "default" must be defined

See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt

 - pinctrl-0	: Pin control group

See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt

 - ranges	: allows valid 1:1 translation between child's address space and

		  parent's address space

Sub-nodes:

The dwc3 core should be added as subnode to ST DWC3 glue as shown in the

example below. The DT binding details of dwc3 can be found in:

Documentation/devicetree/bindings/usb/dwc3.txt

NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value

is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"

or "device".

[1] Documentation/devicetree/bindings/usb/generic.txt

Example:

st_dwc3: dwc3@8f94000 {

	status		= "disabled";

	compatible	= "st,stih407-dwc3";

	reg		= <0x08f94000 0x1000>, <0x110 0x4>;

	reg-names	= "reg-glue", "syscfg-reg";

	st,syscfg	= <&syscfg_core>;

	resets		= <&powerdown STIH407_USB3_POWERDOWN>,

			  <&softreset STIH407_MIPHY2_SOFTRESET>;

	reset-names	= "powerdown",

			  "softreset";

	#address-cells	= <1>;

	#size-cells	= <1>;

	pinctrl-names	= "default";

	pinctrl-0	= <&pinctrl_usb3>;

	ranges;

	dwc3: dwc3@9900000 {

		compatible	= "snps,dwc3";

		reg		= <0x09900000 0x100000>;

		interrupts	= <GIC_SPI 155 IRQ_TYPE_NONE>;

		dr_mode		= "host";

		phys-names      = "usb2-phy", "usb3-phy";

		phys            = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>;

	};

};

	* "fsl,imx23-usbphy" for imx23 and imx28

	* "fsl,imx6q-usbphy" for imx6dq and imx6dl

	* "fsl,imx6sl-usbphy" for imx6sl

	* "fsl,vf610-usbphy" for Vybrid vf610

	* "fsl,imx6sx-usbphy" for imx6sx

  "fsl,imx23-usbphy" is still a fallback for other strings

- reg: Should contain registers location and length