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Commit 20ffa1ca authored by David Woodhouse's avatar David Woodhouse Committed by Thomas Gleixner
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x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support 



Expose indirect_branch_prediction_barrier() for use in subsequent patches.

[ tglx: Add IBPB status to spectre_v2 sysfs file ]

Co-developed-by: default avatarKarimAllah Ahmed <karahmed@amazon.de>
Signed-off-by: default avatarKarimAllah Ahmed <karahmed@amazon.de>
Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Cc: gnomes@lxorguk.ukuu.org.uk
Cc: ak@linux.intel.com
Cc: ashok.raj@intel.com
Cc: dave.hansen@intel.com
Cc: arjan@linux.intel.com
Cc: torvalds@linux-foundation.org
Cc: peterz@infradead.org
Cc: bp@alien8.de
Cc: pbonzini@redhat.com
Cc: tim.c.chen@linux.intel.com
Cc: gregkh@linux-foundation.org
Link: https://lkml.kernel.org/r/1516896855-7642-8-git-send-email-dwmw@amazon.co.uk
parent a5b29663

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -210,6 +210,8 @@ 
#define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */

#define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */

#define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* Fill RSB on context switches */

#define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* Fill RSB on context switches */





#define X86_FEATURE_IBPB		( 7*32+21) /* Indirect Branch Prediction Barrier enabled*/



/* Virtualization flags: Linux defined, word 8 */

/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */

#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */

#define X86_FEATURE_VNMI		( 8*32+ 1) /* Intel Virtual NMI */

#define X86_FEATURE_VNMI		( 8*32+ 1) /* Intel Virtual NMI */

arch/x86/include/asm/nospec-branch.h

+13 −0
Original line number Original line Diff line number Diff line
@@ -218,5 +218,18 @@ static inline void vmexit_fill_RSB(void) 
#endif

#endif

}

}





static inline void indirect_branch_prediction_barrier(void)

{

	asm volatile(ALTERNATIVE("",

				 "movl %[msr], %%ecx\n\t"

				 "movl %[val], %%eax\n\t"

				 "movl $0, %%edx\n\t"

				 "wrmsr",

				 X86_FEATURE_IBPB)

		     : : [msr] "i" (MSR_IA32_PRED_CMD),

			 [val] "i" (PRED_CMD_IBPB)

		     : "eax", "ecx", "edx", "memory");

}



#endif /* __ASSEMBLY__ */

#endif /* __ASSEMBLY__ */

#endif /* __NOSPEC_BRANCH_H__ */
 
#endif /* __NOSPEC_BRANCH_H__ */

arch/x86/kernel/cpu/bugs.c

+9 −1
Original line number Original line Diff line number Diff line
@@ -263,6 +263,13 @@ static void __init spectre_v2_select_mitigation(void) 
		setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);

		setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);

		pr_info("Filling RSB on context switch\n");

		pr_info("Filling RSB on context switch\n");

	}

	}



	/* Initialize Indirect Branch Prediction Barrier if supported */

	if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) ||

	    boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) {

		setup_force_cpu_cap(X86_FEATURE_IBPB);

		pr_info("Enabling Indirect Branch Prediction Barrier\n");

	}

}

}





#undef pr_fmt

#undef pr_fmt
@@ -292,7 +299,8 @@ ssize_t cpu_show_spectre_v2(struct device *dev, 
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))

	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))

		return sprintf(buf, "Not affected\n");

		return sprintf(buf, "Not affected\n");





	return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled],

	return sprintf(buf, "%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],

		       boot_cpu_has(X86_FEATURE_IBPB) ? ", IPBP" : "",

		       spectre_v2_bad_module ? " - vulnerable module loaded" : "");

		       spectre_v2_bad_module ? " - vulnerable module loaded" : "");

}

}

#endif
 
#endif