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Commit 1fea70bc authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.14-2' of... 

Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock changes from Chen-Yu Tsai:

 * Added support for fixed post-divider on divider and NKM-style clocks
 * Added driver for R40 CCU
 * Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
 * Make fractional clock modes really used and correctly configured
 * Make H3 cpu clock rate change correctly to be used with cpufreq

* tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: support R40 SoC
  dt-bindings: add compatible string for Allwinner R40 CCU
  clk: sunxi-ng: nkm: add support for fixed post-divider
  clk: sunxi-ng: div: Add support for fixed post-divider
  dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver
  clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
  clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
  clk: sunxi-ng: Wait for lock when using fractional mode
  clk: sunxi-ng: Make fractional helper less chatty
  clk: sunxi-ng: multiplier: Fix fractional mode
  clk: sunxi-ng: Fix fractional mode for N-M clocks
  clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
parents 4d64556b cd030a78

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+4 −0
Original line number Diff line number Diff line
@@ -3,6 +3,8 @@ Allwinner Clock Control Unit Binding 


Required properties :

- compatible: must contain one of the following compatibles:

		- "allwinner,sun5i-a10s-ccu"

		- "allwinner,sun5i-a13-ccu"

		- "allwinner,sun6i-a31-ccu"

		- "allwinner,sun8i-a23-ccu"

		- "allwinner,sun8i-a33-ccu"
@@ -10,11 +12,13 @@ Required properties : 
		- "allwinner,sun8i-a83t-r-ccu"

		- "allwinner,sun8i-h3-ccu"

		- "allwinner,sun8i-h3-r-ccu"

+		- "allwinner,sun8i-r40-ccu"

		- "allwinner,sun8i-v3s-ccu"

		- "allwinner,sun9i-a80-ccu"

		- "allwinner,sun50i-a64-ccu"

		- "allwinner,sun50i-a64-r-ccu"

		- "allwinner,sun50i-h5-ccu"

		- "nextthing,gr8-ccu"



- reg: Must contain the registers base address and length

- clocks: phandle to the oscillators feeding the CCU. Two are needed:

drivers/clk/sunxi-ng/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -48,6 +48,11 @@ config SUN8I_V3S_CCU 
config SUN8I_DE2_CCU

	bool "Support for the Allwinner SoCs DE2 CCU"



config SUN8I_R40_CCU

	bool "Support for the Allwinner R40 CCU"

	default MACH_SUN8I

	depends on MACH_SUN8I || COMPILE_TEST



config SUN9I_A80_CCU

	bool "Support for the Allwinner A80 CCU"

	default MACH_SUN9I

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o 
obj-$(CONFIG_SUN8I_V3S_CCU)	+= ccu-sun8i-v3s.o

obj-$(CONFIG_SUN8I_DE2_CCU)	+= ccu-sun8i-de2.o

obj-$(CONFIG_SUN8I_R_CCU)	+= ccu-sun8i-r.o

obj-$(CONFIG_SUN8I_R40_CCU)	+= ccu-sun8i-r40.o

obj-$(CONFIG_SUN9I_A80_CCU)	+= ccu-sun9i-a80.o

obj-$(CONFIG_SUN9I_A80_CCU)	+= ccu-sun9i-a80-de.o

obj-$(CONFIG_SUN9I_A80_CCU)	+= ccu-sun9i-a80-usb.o

drivers/clk/sunxi-ng/ccu-sun8i-h3.c

+12 −1
Original line number Diff line number Diff line
@@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 
static const char * const cpux_parents[] = { "osc32k", "osc24M",

					     "pll-cpux" , "pll-cpux" };

static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,

		     0x050, 16, 2, CLK_IS_CRITICAL);

		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);



static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
@@ -1103,6 +1103,13 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = { 
	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),

};



static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {

	.common	= &pll_cpux_clk.common,

	/* copy from pll_cpux_clk */

	.enable	= BIT(31),

	.lock	= BIT(28),

};



static struct ccu_mux_nb sun8i_h3_cpu_nb = {

	.common		= &cpux_clk.common,

	.cm		= &cpux_clk.mux,
@@ -1129,6 +1136,10 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node, 


	sunxi_ccu_probe(node, reg, desc);



	/* Gate then ungate PLL CPU after any rate changes */

	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);



	/* Reparent CPU during PLL CPU rate changes */

	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,

				  &sun8i_h3_cpu_nb);

}

drivers/clk/sunxi-ng/ccu-sun8i-r.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
 */



#ifndef _CCU_SUN8I_R_H

#define _CCU_SUN8I_R_H_

#define _CCU_SUN8I_R_H



#include <dt-bindings/clock/sun8i-r-ccu.h>

#include <dt-bindings/reset/sun8i-r-ccu.h>