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Commit 1fd51d9d authored by Weinan Li's avatar Weinan Li Committed by Joonas Lahtinen
Browse files

drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM 



Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.

v3 : Remove unnecessary comments.
v4 : Separate VM enable patch with GVT-g implementation patch due to code
dependency.
v5 : Use inline for GVT virtual HWSP caps check function.
v6 : Comments refine.

Signed-off-by: default avatarWeinan Li <weinan.z.li@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1508039725-1066-1-git-send-email-weinan.z.li@intel.com
parent 1210d388

drivers/gpu/drm/i915/i915_pvinfo.h

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ enum vgt_g2v_type { 
 * VGT capabilities type

 */

#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)

#define VGT_CAPS_HWSP_EMULATION		BIT(3)



struct vgt_if {

	u64 magic;		/* VGT_MAGIC */

drivers/gpu/drm/i915/i915_vgpu.h

+6 −0
Original line number Diff line number Diff line
@@ -30,6 +30,12 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv); 


bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);



static inline bool

intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)

{

	return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;

}



int intel_vgt_balloon(struct drm_i915_private *dev_priv);

void intel_vgt_deballoon(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_engine_cs.c

+5 −4
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <drm/drm_print.h>



#include "i915_drv.h"

#include "i915_vgpu.h"

#include "intel_ringbuffer.h"

#include "intel_lrc.h"
@@ -386,10 +387,6 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine) 


static bool csb_force_mmio(struct drm_i915_private *i915)

{

	/* GVT emulation depends upon intercepting CSB mmio */

	if (intel_vgpu_active(i915))

		return true;



	/*

	 * IOMMU adds unpredictable latency causing the CSB write (from the

	 * GPU into the HWSP) to only be visible some time after the interrupt
@@ -398,6 +395,10 @@ static bool csb_force_mmio(struct drm_i915_private *i915) 
	if (intel_vtd_active())

		return true;



	/* Older GVT emulation depends upon intercepting CSB mmio */

	if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))

		return true;



	return false;

}

drivers/gpu/drm/i915/intel_lrc.c

+0 −1
Original line number Diff line number Diff line
@@ -793,7 +793,6 @@ static void intel_lrc_irq_handler(unsigned long data) 
			&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];

		unsigned int head, tail;



		/* However GVT emulation depends upon intercepting CSB mmio */

		if (unlikely(execlists->csb_use_mmio)) {

			buf = (u32 * __force)

				(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));