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Commit 1f6e5b25 authored by Paolo Bonzini's avatar Paolo Bonzini Committed by Radim Krčmář
Browse files

KVM: vmx: simplify MSR bitmap setup 



The APICv-enabled MSR bitmap is a superset of the APICv-disabled bitmap.
Make that obvious in vmx_disable_intercept_msr_x2apic.

Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
[Resolved rebase conflict after removing Intel PT. - Radim]
Signed-off-by: default avatarRadim Krčmář <rkrcmar@redhat.com>
parent 07f36616

arch/x86/kvm/vmx.c

+6 −8
Original line number Diff line number Diff line
@@ -5017,14 +5017,13 @@ static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) 
						msr, MSR_TYPE_R | MSR_TYPE_W);

}



static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)

static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_only)

{

	if (apicv_active) {

	__vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,

					msr, type);

	__vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,

					msr, type);

	} else {

	if (!apicv_only) {

		__vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,

				msr, type);

		__vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
@@ -6872,7 +6871,6 @@ static __init int hardware_setup(void) 
	 * TPR reads and writes can be virtualized even if virtual interrupt

	 * delivery is not in use.

	 */

	vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);

	vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);



	/* EOI */