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Commit 1f3b1fd3 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson
Browse files

drm/i915/guc: Update rps.pm_intrmsk_mbz in guc_interrupts_capture/release 



Different state is to be maintained for rps.pm_intrmsk_mbz for GuC and
Execlists. Updating it inside guc_interrupts_* routines as in those
routines GuC load/submission params are sanitized and it should not be set
based on HAS_GUC_SCHED during intel_irq_init.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489199821-6707-3-git-send-email-sagar.a.kamble@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 5dd04556

drivers/gpu/drm/i915/i915_guc_submission.c

+26 −0
Original line number Diff line number Diff line
@@ -954,6 +954,28 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv) 
	I915_WRITE(GUC_BCS_RCS_IER, ~irqs);

	I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);

	I915_WRITE(GUC_WD_VECS_IER, ~irqs);



	/*

	 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all

	 * (unmasked) PM interrupts to the GuC. All other bits of this

	 * register *disable* generation of a specific interrupt.

	 *

	 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when

	 * writing to the PM interrupt mask register, i.e. interrupts

	 * that must not be disabled.

	 *

	 * If the GuC is handling these interrupts, then we must not let

	 * the PM code disable ANY interrupt that the GuC is expecting.

	 * So for each ENABLED (0) bit in this register, we must SET the

	 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.

	 * GuC needs ARAT expired interrupt unmasked hence it is set in

	 * pm_intrmsk_mbz.

	 *

	 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will

	 * result in the register bit being left SET!

	 */

	dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;

	dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_REDIRECT_TO_GUC;

}



int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
@@ -1014,6 +1036,10 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv) 
	I915_WRITE(GUC_BCS_RCS_IER, 0);

	I915_WRITE(GUC_VCS2_VCS1_IER, 0);

	I915_WRITE(GUC_WD_VECS_IER, 0);



	dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;

	dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;



}



void i915_guc_submission_disable(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_irq.c

+0 −24
Original line number Diff line number Diff line
@@ -4284,30 +4284,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 
	if (INTEL_INFO(dev_priv)->gen >= 8)

		dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;



	/*

	 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all

	 * (unmasked) PM interrupts to the GuC. All other bits of this

	 * register *disable* generation of a specific interrupt.

	 *

	 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when

	 * writing to the PM interrupt mask register, i.e. interrupts

	 * that must not be disabled.

	 *

	 * If the GuC is handling these interrupts, then we must not let

	 * the PM code disable ANY interrupt that the GuC is expecting.

	 * So for each ENABLED (0) bit in this register, we must SET the

	 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.

	 * GuC needs ARAT expired interrupt unmasked hence it is set in

	 * pm_intrmsk_mbz.

	 *

	 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will

	 * result in the register bit being left SET!

	 */

	if (HAS_GUC_SCHED(dev_priv)) {

		dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;

		dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_REDIRECT_TO_GUC;

	}



	if (IS_GEN2(dev_priv)) {

		/* Gen2 doesn't have a hardware frame counter */

		dev->max_vblank_count = 0;