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Commit 1df7addb authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
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MIPS: ralink: add MT7621 support 



MT7621 is based on a 1004k core. This patch adds support for the SoC. The
timer and IRQ is just boiler plate as GIC has recently been moved to
generic places in the kernel and just works.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11990/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 2761f83c

arch/mips/include/asm/mach-ralink/irq.h

0 → 100644
+9 −0
Original line number Diff line number Diff line 
#ifndef __ASM_MACH_RALINK_IRQ_H

#define __ASM_MACH_RALINK_IRQ_H



#define GIC_NUM_INTRS	64

#define NR_IRQS 256



#include_next <irq.h>



#endif

arch/mips/include/asm/mach-ralink/mt7621.h

0 → 100644
+38 −0
Original line number Diff line number Diff line 
/*

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published

 * by the Free Software Foundation.

 *

 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>

 */



#ifndef _MT7621_REGS_H_

#define _MT7621_REGS_H_



#define MT7621_PALMBUS_BASE		0x1C000000

#define MT7621_PALMBUS_SIZE		0x03FFFFFF



#define MT7621_SYSC_BASE		0x1E000000



#define SYSC_REG_CHIP_NAME0		0x00

#define SYSC_REG_CHIP_NAME1		0x04

#define SYSC_REG_CHIP_REV		0x0c

#define SYSC_REG_SYSTEM_CONFIG0		0x10

#define SYSC_REG_SYSTEM_CONFIG1		0x14



#define CHIP_REV_PKG_MASK		0x1

#define CHIP_REV_PKG_SHIFT		16

#define CHIP_REV_VER_MASK		0xf

#define CHIP_REV_VER_SHIFT		8

#define CHIP_REV_ECO_MASK		0xf



#define MT7621_DRAM_BASE                0x0

#define MT7621_DDR2_SIZE_MIN		32

#define MT7621_DDR2_SIZE_MAX		256



#define MT7621_CHIP_NAME0		0x3637544D

#define MT7621_CHIP_NAME1		0x20203132



#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)



#endif

arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h

0 → 100644
+65 −0
Original line number Diff line number Diff line 
/*

 * Ralink MT7621 specific CPU feature overrides

 *

 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>

 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

 * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>

 *

 * This file was derived from: include/asm-mips/cpu-features.h

 *	Copyright (C) 2003, 2004 Ralf Baechle

 *	Copyright (C) 2004 Maciej W. Rozycki

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published

 * by the Free Software Foundation.

 *

 */

#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H

#define _MT7621_CPU_FEATURE_OVERRIDES_H



#define cpu_has_tlb		1

#define cpu_has_4kex		1

#define cpu_has_3k_cache	0

#define cpu_has_4k_cache	1

#define cpu_has_tx39_cache	0

#define cpu_has_sb1_cache	0

#define cpu_has_fpu		0

#define cpu_has_32fpr		0

#define cpu_has_counter		1

#define cpu_has_watch		1

#define cpu_has_divec		1



#define cpu_has_prefetch	1

#define cpu_has_ejtag		1

#define cpu_has_llsc		1



#define cpu_has_mips16		1

#define cpu_has_mdmx		0

#define cpu_has_mips3d		0

#define cpu_has_smartmips	0



#define cpu_has_mips32r1	1

#define cpu_has_mips32r2	1

#define cpu_has_mips64r1	0

#define cpu_has_mips64r2	0



#define cpu_has_dsp		1

#define cpu_has_dsp2		0

#define cpu_has_mipsmt		1



#define cpu_has_64bits		0

#define cpu_has_64bit_zero_reg	0

#define cpu_has_64bit_gp_regs	0

#define cpu_has_64bit_addresses	0



#define cpu_dcache_line_size()	32

#define cpu_icache_line_size()	32



#define cpu_has_dc_aliases	0

#define cpu_has_vtag_icache	0



#define cpu_has_rixi		0

#define cpu_has_tlbinv		0

#define cpu_has_userlocal	1



#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */

arch/mips/ralink/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ config RALINK_ILL_ACC 
config IRQ_INTC

	bool

	default y

	depends on !SOC_MT7621



choice

	prompt "Ralink SoC selection"
@@ -38,6 +39,16 @@ choice 
	config SOC_MT7620

		bool "MT7620/8"



	config SOC_MT7621

		bool "MT7621"

		select MIPS_CPU_SCACHE

		select SYS_SUPPORTS_MULTITHREADING

		select SYS_SUPPORTS_SMP

		select SYS_SUPPORTS_MIPS_CPS

		select MIPS_GIC

		select COMMON_CLK

		select CLKSRC_MIPS_GIC

		select HW_HAS_PCI

endchoice



choice

arch/mips/ralink/Makefile

+7 −1
Original line number Diff line number Diff line
@@ -6,18 +6,24 @@ 
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>

# Copyright (C) 2013 John Crispin <blogic@openwrt.org>



obj-y := prom.o of.o reset.o clk.o irq.o timer.o

obj-y := prom.o of.o reset.o



ifndef CONFIG_MIPS_GIC

	obj-y += clk.o timer.o

endif



obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o



obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o



obj-$(CONFIG_IRQ_INTC) += irq.o

obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o



obj-$(CONFIG_SOC_RT288X) += rt288x.o

obj-$(CONFIG_SOC_RT305X) += rt305x.o

obj-$(CONFIG_SOC_RT3883) += rt3883.o

obj-$(CONFIG_SOC_MT7620) += mt7620.o

obj-$(CONFIG_SOC_MT7621) += mt7621.o



obj-$(CONFIG_EARLY_PRINTK) += early_printk.o