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Commit 1dba99f4 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Rename intel_flush_display_plane to intel_flush_primary_plane 



The intel_flush_primary_plane name actually tells us which plane
we're talking about.

Also reorganize the internals a bit and add a missing POSTING_READ()
to make sure the hardware has seen the changes by the time we
return from the function.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 20bc8673

drivers/gpu/drm/i915/intel_display.c

+8 −8
Original line number Diff line number Diff line
@@ -1812,13 +1812,13 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, 
 * Plane regs are double buffered, going from enabled->disabled needs a

 * trigger in order to latch.  The display address reg provides this.

 */

void intel_flush_display_plane(struct drm_i915_private *dev_priv,

void intel_flush_primary_plane(struct drm_i915_private *dev_priv,

			       enum plane plane)

{

	if (dev_priv->info->gen >= 4)

		I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));

	else

		I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));

	u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);



	I915_WRITE(reg, I915_READ(reg));

	POSTING_READ(reg);

}



/**
@@ -1848,7 +1848,7 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, 
		return;



	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);

	intel_flush_display_plane(dev_priv, plane);

	intel_flush_primary_plane(dev_priv, plane);

	intel_wait_for_vblank(dev_priv->dev, pipe);

}
@@ -1876,7 +1876,7 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv, 
		return;



	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);

	intel_flush_display_plane(dev_priv, plane);

	intel_flush_primary_plane(dev_priv, plane);

	intel_wait_for_vblank(dev_priv->dev, pipe);

}

drivers/gpu/drm/i915/intel_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -811,7 +811,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 


/* intel_sprite.c */

int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);

void intel_flush_display_plane(struct drm_i915_private *dev_priv,

void intel_flush_primary_plane(struct drm_i915_private *dev_priv,

			       enum plane plane);

void intel_plane_restore(struct drm_plane *plane);

void intel_plane_disable(struct drm_plane *plane);

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -4773,7 +4773,7 @@ static void g4x_disable_trickle_feed(struct drm_device *dev) 
		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

		intel_flush_primary_plane(dev_priv, pipe);

	}

}

drivers/gpu/drm/i915/intel_tv.c

+2 −2
Original line number Diff line number Diff line
@@ -1094,7 +1094,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder) 
		unsigned int xsize, ysize;

		/* Pipe must be off here */

		I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);

		intel_flush_display_plane(dev_priv, intel_crtc->plane);

		intel_flush_primary_plane(dev_priv, intel_crtc->plane);



		/* Wait for vblank for the disable to take effect */

		if (IS_GEN2(dev))
@@ -1123,7 +1123,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder) 


		I915_WRITE(pipeconf_reg, pipeconf);

		I915_WRITE(dspcntr_reg, dspcntr);

		intel_flush_display_plane(dev_priv, intel_crtc->plane);

		intel_flush_primary_plane(dev_priv, intel_crtc->plane);

	}



	j = 0;