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Commit 1c75c421 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'socfpga/hw' into next/soc 



From Dinh Nguyen, this is a series of patches introducing support for
socfpga hardware (Altera Cyclone5). It also includes a cleanup that
moves some of the ARMv7 cache maintenance functions to a common location,
since three other platforms aready implemented it separately.

* socfpga/hw:
  arm: socfpga: Add SMP support for actual socfpga harware
  arm: Add v7_invalidate_l1 to cache-v7.S
  arm: socfpga: Add entries to enable make dtbs socfpga
  arm: socfpga: Add new device tree source for actual socfpga HW

Trivial conflict in arch/arm/mach-tegra/headsmp.S.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 877cd953 d6dd735f

Documentation/devicetree/bindings/arm/altera/socfpga-system.txt

+2 −0
Original line number Original line Diff line number Diff line
@@ -3,9 +3,11 @@ Altera SOCFPGA System Manager 
Required properties:

Required properties:

- compatible : "altr,sys-mgr"

- compatible : "altr,sys-mgr"

- reg : Should contain 1 register ranges(address and length)

- reg : Should contain 1 register ranges(address and length)

- cpu1-start-addr : CPU1 start address in hex.





Example:

Example:

	 sysmgr@ffd08000 {

	 sysmgr@ffd08000 {

		compatible = "altr,sys-mgr";

		compatible = "altr,sys-mgr";

		reg = <0xffd08000 0x1000>;

		reg = <0xffd08000 0x1000>;

		cpu1-start-addr = <0xffd080c4>;

	};
 
	};

arch/arm/boot/dts/Makefile

+2 −0
Original line number Original line Diff line number Diff line
@@ -125,6 +125,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 
	r8a7740-armadillo800eva.dtb \

	r8a7740-armadillo800eva.dtb \

	sh73a0-kzm9g.dtb \

	sh73a0-kzm9g.dtb \

	sh7372-mackerel.dtb

	sh7372-mackerel.dtb

dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \

	socfpga_vt.dtb

dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \

dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \

	spear1340-evb.dtb

	spear1340-evb.dtb

dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \

dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \

arch/arm/boot/dts/socfpga.dtsi

+10 −12
Original line number Original line Diff line number Diff line
@@ -25,6 +25,10 @@ 
		ethernet0 = &gmac0;

		ethernet0 = &gmac0;

		serial0 = &uart0;

		serial0 = &uart0;

		serial1 = &uart1;

		serial1 = &uart1;

		timer0 = &timer0;

		timer1 = &timer1;

		timer2 = &timer2;

		timer3 = &timer3;

	};

	};





	cpus {

	cpus {
@@ -98,47 +102,41 @@ 
			interrupts = <1 13 0xf04>;

			interrupts = <1 13 0xf04>;

		};

		};





		timer0: timer@ffc08000 {

		timer0: timer0@ffc08000 {

			compatible = "snps,dw-apb-timer-sp";

			compatible = "snps,dw-apb-timer-sp";

			interrupts = <0 167 4>;

			interrupts = <0 167 4>;

			clock-frequency = <200000000>;

			reg = <0xffc08000 0x1000>;

			reg = <0xffc08000 0x1000>;

		};

		};





		timer1: timer@ffc09000 {

		timer1: timer1@ffc09000 {

			compatible = "snps,dw-apb-timer-sp";

			compatible = "snps,dw-apb-timer-sp";

			interrupts = <0 168 4>;

			interrupts = <0 168 4>;

			clock-frequency = <200000000>;

			reg = <0xffc09000 0x1000>;

			reg = <0xffc09000 0x1000>;

		};

		};





		timer2: timer@ffd00000 {

		timer2: timer2@ffd00000 {

			compatible = "snps,dw-apb-timer-osc";

			compatible = "snps,dw-apb-timer-osc";

			interrupts = <0 169 4>;

			interrupts = <0 169 4>;

			clock-frequency = <200000000>;

			reg = <0xffd00000 0x1000>;

			reg = <0xffd00000 0x1000>;

		};

		};





		timer3: timer@ffd01000 {

		timer3: timer3@ffd01000 {

			compatible = "snps,dw-apb-timer-osc";

			compatible = "snps,dw-apb-timer-osc";

			interrupts = <0 170 4>;

			interrupts = <0 170 4>;

			clock-frequency = <200000000>;

			reg = <0xffd01000 0x1000>;

			reg = <0xffd01000 0x1000>;

		};

		};





		uart0: uart@ffc02000 {

		uart0: serial0@ffc02000 {

			compatible = "snps,dw-apb-uart";

			compatible = "snps,dw-apb-uart";

			reg = <0xffc02000 0x1000>;

			reg = <0xffc02000 0x1000>;

			clock-frequency = <7372800>;

			interrupts = <0 162 4>;

			interrupts = <0 162 4>;

			reg-shift = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			reg-io-width = <4>;

		};

		};





		uart1: uart@ffc03000 {

		uart1: serial1@ffc03000 {

			compatible = "snps,dw-apb-uart";

			compatible = "snps,dw-apb-uart";

			reg = <0xffc03000 0x1000>;

			reg = <0xffc03000 0x1000>;

			clock-frequency = <7372800>;

			interrupts = <0 163 4>;

			interrupts = <0 163 4>;

			reg-shift = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			reg-io-width = <4>;

arch/arm/boot/dts/socfpga_cyclone5.dts

+32 −2
Original line number Original line Diff line number Diff line
@@ -20,7 +20,7 @@ 




/ {

/ {

	model = "Altera SOCFPGA Cyclone V";

	model = "Altera SOCFPGA Cyclone V";

	compatible = "altr,socfpga-cyclone5";

	compatible = "altr,socfpga-cyclone5", "altr,socfpga";





	chosen {

	chosen {

		bootargs = "console=ttyS0,57600";

		bootargs = "console=ttyS0,57600";
@@ -29,6 +29,36 @@ 
	memory {

	memory {

		name = "memory";

		name = "memory";

		device_type = "memory";

		device_type = "memory";

		reg = <0x0 0x10000000>; /* 256MB */

		reg = <0x0 0x40000000>; /* 1GB */

	};



	soc {

		timer0@ffc08000 {

			clock-frequency = <100000000>;

		};



		timer1@ffc09000 {

			clock-frequency = <100000000>;

		};



		timer2@ffd00000 {

			clock-frequency = <25000000>;

		};



		timer3@ffd01000 {

			clock-frequency = <25000000>;

		};



		serial0@ffc02000 {

			clock-frequency = <100000000>;

		};



		serial1@ffc03000 {

			clock-frequency = <100000000>;

		};



		sysmgr@ffd08000 {

			cpu1-start-addr = <0xffd080c4>;

		};

	};

	};

};
 
};

arch/arm/boot/dts/socfpga_vt.dts

0 → 100644
+64 −0
Original line number Original line Diff line number Diff line 
/*

 *  Copyright (C) 2013 Altera Corporation <www.altera.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



/dts-v1/;

/include/ "socfpga.dtsi"



/ {

	model = "Altera SOCFPGA VT";

	compatible = "altr,socfpga-vt", "altr,socfpga";



	chosen {

		bootargs = "console=ttyS0,57600";

	};



	memory {

		name = "memory";

		device_type = "memory";

		reg = <0x0 0x40000000>; /* 1 GB */

	};



	soc {

		timer0@ffc08000 {

			clock-frequency = <7000000>;

		};



		timer1@ffc09000 {

			clock-frequency = <7000000>;

		};



		timer2@ffd00000 {

			clock-frequency = <7000000>;

		};



		timer3@ffd01000 {

			clock-frequency = <7000000>;

		};



		serial0@ffc02000 {

			clock-frequency = <7372800>;

		};



		serial1@ffc03000 {

			clock-frequency = <7372800>;

		};



		sysmgr@ffd08000 {

			cpu1-start-addr = <0xffd08010>;

		};

	};

};