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Commit 1bf0bc1e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc 

From Simon Horman <horms@verge.net.au>:
  This series is based on the renesas/soc branch of the arm-soc tree.
  There will be a subquent 'SoC2' pull request which is based on this
  pull-request and a pull-request for boards.

* 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: shmobile: add fsi external clock sh7372
  ARM: shmobile: add fsi external clock on r8a7740
  ARM: shmobile: r8a7740: add FSI-DVI clocks
  ARM: shmobile: sh7372: use sh_clk_fsidiv_register() for FSI-DIV clocks
  ARM: shmobile: sh7372: sh7372_fsidivX_clk become non-global
  sh: clkfwk: add sh_clk_fsidiv_register()
  ARM: shmobile: r8a7779: add USB OHCI clock support
  ARM: shmobile: r8a7779: add USB EHCI clock support
  ARM: shmobile: r8a7740: add USB24 clock explain
  ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents b68c50d8 29446286

arch/arm/mach-shmobile/board-ap4evb.c

+1 −1
Original line number Diff line number Diff line
@@ -728,7 +728,7 @@ static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable) 
static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)

{

	struct clk *fsib_clk;

	struct clk *fdiv_clk = &sh7372_fsidivb_clk;

	struct clk *fdiv_clk = clk_get(NULL, "fsidivb");

	long fsib_rate = 0;

	long fdiv_rate = 0;

	int ackmd_bpfmd;

arch/arm/mach-shmobile/board-mackerel.c

+1 −1
Original line number Diff line number Diff line
@@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable) 
static int fsi_b_set_rate(struct device *dev, int rate, int enable)

{

	struct clk *fsib_clk;

	struct clk *fdiv_clk = &sh7372_fsidivb_clk;

	struct clk *fdiv_clk = clk_get(NULL, "fsidivb");

	long fsib_rate = 0;

	long fdiv_rate = 0;

	int ackmd_bpfmd;

arch/arm/mach-shmobile/clock-r8a7740.c

+34 −0
Original line number Diff line number Diff line
@@ -65,6 +65,9 @@ 
#define SMSTPCR3	IOMEM(0xe615013c)

#define SMSTPCR4	IOMEM(0xe6150140)



#define FSIDIVA		IOMEM(0xFE1F8000)

#define FSIDIVB		IOMEM(0xFE1F8008)



/* Fixed 32 KHz root clock from EXTALR pin */

static struct clk extalr_clk = {

	.rate	= 32768,
@@ -188,6 +191,22 @@ static struct clk pllc1_div2_clk = { 
};



/* USB clock */

/*

 * USBCKCR is controlling usb24 clock

 * bit[7] : parent clock

 * bit[6] : clock divide rate

 * And this bit[7] is used as a "usb24s" from other devices.

 * (Video clock / Sub clock / SPU clock)

 * You can controll this clock as a below.

 *

 * struct clk *usb24	= clk_get(dev,  "usb24");

 * struct clk *usb24s	= clk_get(NULL, "usb24s");

 * struct clk *system	= clk_get(NULL, "system_clk");

 * int rate = clk_get_rate(system);

 *

 * clk_set_parent(usb24s, system);  // for bit[7]

 * clk_set_rate(usb24, rate / 2);   // for bit[6]

 */

static struct clk *usb24s_parents[] = {

	[0] = &system_clk,

	[1] = &extal2_clk
@@ -427,6 +446,14 @@ static struct clk *late_main_clks[] = { 
	&hdmi2_clk,

};



/* FSI DIV */

enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };



static struct clk fsidivs[] = {

	[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),

	[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),

};



/* MSTP */

enum {

	DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
@@ -596,6 +623,10 @@ static struct clk_lookup lookups[] = { 


	CLKDEV_ICK_ID("icka", "sh_fsi2",	&div6_reparent_clks[DIV6_FSIA]),

	CLKDEV_ICK_ID("ickb", "sh_fsi2",	&div6_reparent_clks[DIV6_FSIB]),

	CLKDEV_ICK_ID("diva", "sh_fsi2",	&fsidivs[FSIDIV_A]),

	CLKDEV_ICK_ID("divb", "sh_fsi2",	&fsidivs[FSIDIV_B]),

	CLKDEV_ICK_ID("xcka", "sh_fsi2",	&fsiack_clk),

	CLKDEV_ICK_ID("xckb", "sh_fsi2",	&fsibck_clk),

};



void __init r8a7740_clock_init(u8 md_ck)
@@ -641,6 +672,9 @@ void __init r8a7740_clock_init(u8 md_ck) 
	for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)

		ret = clk_register(late_main_clks[k]);



	if (!ret)

		ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);



	clkdev_add_table(lookups, ARRAY_SIZE(lookups));



	if (!ret)

arch/arm/mach-shmobile/clock-r8a7779.c

+7 −0
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = { 
};



enum { MSTP323, MSTP322, MSTP321, MSTP320,

	MSTP101, MSTP100,

	MSTP030,

	MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,

	MSTP016, MSTP015, MSTP014,
@@ -98,6 +99,8 @@ static struct clk mstp_clks[MSTP_NR] = { 
	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */

	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */

	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */

	[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */

	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */

	[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */

	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */

	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
@@ -153,6 +156,10 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_CON_ID("peripheral_clk",	&div4_clks[DIV4_P]),



	/* MSTP32 clocks */

	CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */

	CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */

	CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */

	CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */

	CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */

	CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */

	CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */

arch/arm/mach-shmobile/clock-sh7372.c

+12 −82
Original line number Diff line number Diff line
@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 
};



/* FSI DIV */

static unsigned long fsidiv_recalc(struct clk *clk)

{

	unsigned long value;



	value = __raw_readl(clk->mapping->base);



	value >>= 16;

	if (value < 2)

		return 0;



	return clk->parent->rate / value;

}



static long fsidiv_round_rate(struct clk *clk, unsigned long rate)

{

	return clk_rate_div_range_round(clk, 2, 0xffff, rate);

}



static void fsidiv_disable(struct clk *clk)

{

	__raw_writel(0, clk->mapping->base);

}



static int fsidiv_enable(struct clk *clk)

{

	unsigned long value;



	value  = __raw_readl(clk->mapping->base) >> 16;

	if (value < 2)

		return -EIO;



	__raw_writel((value << 16) | 0x3, clk->mapping->base);



	return 0;

}



static int fsidiv_set_rate(struct clk *clk, unsigned long rate)

{

	int idx;



	idx = (clk->parent->rate / rate) & 0xffff;

	if (idx < 2)

		return -EINVAL;



	__raw_writel(idx << 16, clk->mapping->base);

	return 0;

}



static struct sh_clk_ops fsidiv_clk_ops = {

	.recalc		= fsidiv_recalc,

	.round_rate	= fsidiv_round_rate,

	.set_rate	= fsidiv_set_rate,

	.enable		= fsidiv_enable,

	.disable	= fsidiv_disable,

};



static struct clk_mapping fsidiva_clk_mapping = {

	.phys	= FSIDIVA,

	.len	= 8,

};



struct clk sh7372_fsidiva_clk = {

	.ops		= &fsidiv_clk_ops,

	.parent		= &div6_reparent_clks[DIV6_FSIA], /* late install */

	.mapping	= &fsidiva_clk_mapping,

};

enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };



static struct clk_mapping fsidivb_clk_mapping = {

	.phys	= FSIDIVB,

	.len	= 8,

};



struct clk sh7372_fsidivb_clk = {

	.ops		= &fsidiv_clk_ops,

	.parent		= &div6_reparent_clks[DIV6_FSIB],  /* late install */

	.mapping	= &fsidivb_clk_mapping,

};



static struct clk *late_main_clks[] = {

	&sh7372_fsidiva_clk,

	&sh7372_fsidivb_clk,

static struct clk fsidivs[] = {

	[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),

	[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),

};



enum { MSTP001, MSTP000,
@@ -583,6 +507,8 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),

	CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),

	CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),

	CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),

	CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),



	/* DIV4 clocks */

	CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -678,6 +604,10 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),

	CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),

	CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),

	CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),

	CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),

	CLKDEV_ICK_ID("xcka", "sh_fsi2", &sh7372_fsiack_clk),

	CLKDEV_ICK_ID("xckb", "sh_fsi2", &sh7372_fsibck_clk),

};



void __init sh7372_clock_init(void)
@@ -706,8 +636,8 @@ void __init sh7372_clock_init(void) 
	if (!ret)

		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);



	for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)

		ret = clk_register(late_main_clks[k]);

	if (!ret)

		ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);



	clkdev_add_table(lookups, ARRAY_SIZE(lookups));