Merge branch 'for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata (1bc03573) · Commits · e / devices / android_kernel_teracube_emerald

Documentation/devicetree/bindings/ata/ahci-ceva.txt

+39 −0

Original line number	Original line	Diff line number	Diff line
	@@ -5,6 +5,36 @@ Required properties:
	- compatible: Compatibility string. Must be 'ceva,ahci-1v84'.		- compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
	- clocks: Input clock specifier. Refer to common clock bindings.		- clocks: Input clock specifier. Refer to common clock bindings.
	- interrupts: Interrupt specifier. Refer to interrupt binding.		- interrupts: Interrupt specifier. Refer to interrupt binding.
			- ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
			- ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
			The fields for the above parameter must be as shown below:
			ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
			CINMP : COMINIT Negate Minimum Period.
			CIBGN : COMINIT Burst Gap Nominal.
			CIBGMX: COMINIT Burst Gap Maximum.
			CIBGMN: COMINIT Burst Gap Minimum.
			- ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
			- ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
			The fields for the above parameter must be as shown below:
			ceva,pN-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
			CWBGMN: COMWAKE Burst Gap Minimum.
			CWBGMX: COMWAKE Burst Gap Maximum.
			CWBGN: COMWAKE Burst Gap Nominal.
			CWNMP: COMWAKE Negate Minimum Period.
			- ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
			- ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
			The fields for the above parameter must be as shown below:
			ceva,pN-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
			BMX: COM Burst Maximum.
			BNM: COM Burst Nominal.
			SFD: Signal Failure Detection value.
			PTST: Partial to Slumber timer value.
			- ceva,p0-retry-params: Retry interval timing value for port 0.
			- ceva,p1-retry-params: Retry interval timing value for port 1.
			The fields for the above parameter must be as shown below:
			ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
			RIT: Retry Interval Timer.
			RCT: Rate Change Timer.

	Optional properties:		Optional properties:
	- ceva,broken-gen2: limit to gen1 speed instead of gen2.		- ceva,broken-gen2: limit to gen1 speed instead of gen2.
	@@ -16,5 +46,14 @@ Examples:
	interrupt-parent = <&gic>;		interrupt-parent = <&gic>;
	interrupts = <0 133 4>;		interrupts = <0 133 4>;
	clocks = <&clkc SATA_CLK_ID>;		clocks = <&clkc SATA_CLK_ID>;
			ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
			ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
			ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
			ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;

			ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
			ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
			ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
			ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
	ceva,broken-gen2;		ceva,broken-gen2;
	};		};

drivers/ata/ahci.c

+7 −2

Original line number	Original line	Diff line number	Diff line
	@@ -57,6 +57,7 @@ enum {
	AHCI_PCI_BAR_STA2X11 = 0,		AHCI_PCI_BAR_STA2X11 = 0,
	AHCI_PCI_BAR_CAVIUM = 0,		AHCI_PCI_BAR_CAVIUM = 0,
	AHCI_PCI_BAR_ENMOTUS = 2,		AHCI_PCI_BAR_ENMOTUS = 2,
			AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
	AHCI_PCI_BAR_STANDARD = 5,		AHCI_PCI_BAR_STANDARD = 5,
	};		};

	@@ -1570,8 +1571,12 @@ static int ahci_init_one(struct pci_dev pdev, const struct pci_device_id ent)
	ahci_pci_bar = AHCI_PCI_BAR_STA2X11;		ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
	else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)		else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
	ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;		ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
	else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)		else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
			if (pdev->device == 0xa01c)
	ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;		ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
			if (pdev->device == 0xa084)
			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
			}

	/* acquire resources */		/* acquire resources */
	rc = pcim_enable_device(pdev);		rc = pcim_enable_device(pdev);

drivers/ata/ahci_ceva.c

+159 −38

Original line number	Original line	Diff line number	Diff line
	@@ -32,15 +32,27 @@
	#define AHCI_VEND_PP3C 0xB0		#define AHCI_VEND_PP3C 0xB0
	#define AHCI_VEND_PP4C 0xB4		#define AHCI_VEND_PP4C 0xB4
	#define AHCI_VEND_PP5C 0xB8		#define AHCI_VEND_PP5C 0xB8
			#define AHCI_VEND_AXICC 0xBC
	#define AHCI_VEND_PAXIC 0xC0		#define AHCI_VEND_PAXIC 0xC0
	#define AHCI_VEND_PTC 0xC8		#define AHCI_VEND_PTC 0xC8

	/* Vendor Specific Register bit definitions */		/* Vendor Specific Register bit definitions */
	#define PAXIC_ADBW_BW64 0x1		#define PAXIC_ADBW_BW64 0x1
	#define PAXIC_MAWIDD (1 << 8)		#define PAXIC_MAWID(i) (((i) * 2) << 4)
	#define PAXIC_MARIDD (1 << 16)		#define PAXIC_MARID(i) (((i) * 2) << 12)
			#define PAXIC_MARIDD(i) ((((i) * 2) + 1) << 16)
			#define PAXIC_MAWIDD(i) ((((i) * 2) + 1) << 8)
	#define PAXIC_OTL (0x4 << 20)		#define PAXIC_OTL (0x4 << 20)

			/* Register bit definitions for cache control */
			#define AXICC_ARCA_VAL (0xF << 0)
			#define AXICC_ARCF_VAL (0xF << 4)
			#define AXICC_ARCH_VAL (0xF << 8)
			#define AXICC_ARCP_VAL (0xF << 12)
			#define AXICC_AWCFD_VAL (0xF << 16)
			#define AXICC_AWCD_VAL (0xF << 20)
			#define AXICC_AWCF_VAL (0xF << 24)

	#define PCFG_TPSS_VAL (0x32 << 16)		#define PCFG_TPSS_VAL (0x32 << 16)
	#define PCFG_TPRS_VAL (0x2 << 12)		#define PCFG_TPRS_VAL (0x2 << 12)
	#define PCFG_PAD_VAL 0x2		#define PCFG_PAD_VAL 0x2
	@@ -50,21 +62,6 @@
	#define PPCFG_PSS_EN (1 << 29)		#define PPCFG_PSS_EN (1 << 29)
	#define PPCFG_ESDF_EN (1 << 31)		#define PPCFG_ESDF_EN (1 << 31)

	#define PP2C_CIBGMN 0x0F
	#define PP2C_CIBGMX (0x25 << 8)
	#define PP2C_CIBGN (0x18 << 16)
	#define PP2C_CINMP (0x29 << 24)

	#define PP3C_CWBGMN 0x04
	#define PP3C_CWBGMX (0x0B << 8)
	#define PP3C_CWBGN (0x08 << 16)
	#define PP3C_CWNMP (0x0F << 24)

	#define PP4C_BMX 0x0a
	#define PP4C_BNM (0x08 << 8)
	#define PP4C_SFD (0x4a << 16)
	#define PP4C_PTST (0x06 << 24)

	#define PP5C_RIT 0x60216		#define PP5C_RIT 0x60216
	#define PP5C_RCT (0x7f0 << 20)		#define PP5C_RCT (0x7f0 << 20)

	@@ -75,6 +72,7 @@
	#define PORT1_BASE 0x180		#define PORT1_BASE 0x180

	/* Port Control Register Bit Definitions */		/* Port Control Register Bit Definitions */
			#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
	#define PORT_SCTL_SPD_GEN2 (0x2 << 4)		#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
	#define PORT_SCTL_SPD_GEN1 (0x1 << 4)		#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
	#define PORT_SCTL_IPM (0x3 << 8)		#define PORT_SCTL_IPM (0x3 << 8)
	@@ -85,13 +83,43 @@
	#define DRV_NAME "ahci-ceva"		#define DRV_NAME "ahci-ceva"
	#define CEVA_FLAG_BROKEN_GEN2 1		#define CEVA_FLAG_BROKEN_GEN2 1

			static unsigned int rx_watermark = PTC_RX_WM_VAL;
			module_param(rx_watermark, uint, 0644);
			MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");

	struct ceva_ahci_priv {		struct ceva_ahci_priv {
	struct platform_device *ahci_pdev;		struct platform_device *ahci_pdev;
			/* Port Phy2Cfg Register */
			u32 pp2c[NR_PORTS];
			u32 pp3c[NR_PORTS];
			u32 pp4c[NR_PORTS];
			u32 pp5c[NR_PORTS];
			/* Axi Cache Control Register */
			u32 axicc;
			bool is_cci_enabled;
	int flags;		int flags;
	};		};

			static unsigned int ceva_ahci_read_id(struct ata_device *dev,
			struct ata_taskfile tf, u16 id)
			{
			u32 err_mask;

			err_mask = ata_do_dev_read_id(dev, tf, id);
			if (err_mask)
			return err_mask;
			/*
			* Since CEVA controller does not support device sleep feature, we
			* need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data.
			*/
			id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));

			return 0;
			}

	static struct ata_port_operations ahci_ceva_ops = {		static struct ata_port_operations ahci_ceva_ops = {
	.inherits = &ahci_platform_ops,		.inherits = &ahci_platform_ops,
			.read_id = ceva_ahci_read_id,
	};		};

	static const struct ata_port_info ahci_ceva_port_info = {		static const struct ata_port_info ahci_ceva_port_info = {
	@@ -108,14 +136,6 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
	u32 tmp;		u32 tmp;
	int i;		int i;

	/*
	* AXI Data bus width to 64
	* Set Mem Addr Read, Write ID for data transfers
	* Transfer limit to 72 DWord
	*/
	tmp = PAXIC_ADBW_BW64 \| PAXIC_MAWIDD \| PAXIC_MARIDD \| PAXIC_OTL;
	writel(tmp, mmio + AHCI_VEND_PAXIC);

	/* Set AHCI Enable */		/* Set AHCI Enable */
	tmp = readl(mmio + HOST_CTL);		tmp = readl(mmio + HOST_CTL);
	tmp \|= HOST_AHCI_EN;		tmp \|= HOST_AHCI_EN;
	@@ -126,32 +146,48 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
	tmp = PCFG_TPSS_VAL \| PCFG_TPRS_VAL \| (PCFG_PAD_VAL + i);		tmp = PCFG_TPSS_VAL \| PCFG_TPRS_VAL \| (PCFG_PAD_VAL + i);
	writel(tmp, mmio + AHCI_VEND_PCFG);		writel(tmp, mmio + AHCI_VEND_PCFG);

			/*
			* AXI Data bus width to 64
			* Set Mem Addr Read, Write ID for data transfers
			* Set Mem Addr Read ID, Write ID for non-data transfers
			* Transfer limit to 72 DWord
			*/
			tmp = PAXIC_ADBW_BW64 \| PAXIC_MAWIDD(i) \| PAXIC_MARIDD(i) \|
			PAXIC_MAWID(i) \| PAXIC_MARID(i) \| PAXIC_OTL;
			writel(tmp, mmio + AHCI_VEND_PAXIC);

			/* Set AXI cache control register if CCi is enabled */
			if (cevapriv->is_cci_enabled) {
			tmp = readl(mmio + AHCI_VEND_AXICC);
			tmp \|= AXICC_ARCA_VAL \| AXICC_ARCF_VAL \|
			AXICC_ARCH_VAL \| AXICC_ARCP_VAL \|
			AXICC_AWCFD_VAL \| AXICC_AWCD_VAL \|
			AXICC_AWCF_VAL;
			writel(tmp, mmio + AHCI_VEND_AXICC);
			}

	/* Port Phy Cfg register enables */		/* Port Phy Cfg register enables */
	tmp = PPCFG_TTA \| PPCFG_PSS_EN \| PPCFG_ESDF_EN;		tmp = PPCFG_TTA \| PPCFG_PSS_EN \| PPCFG_ESDF_EN;
	writel(tmp, mmio + AHCI_VEND_PPCFG);		writel(tmp, mmio + AHCI_VEND_PPCFG);

	/* Phy Control OOB timing parameters COMINIT */		/* Phy Control OOB timing parameters COMINIT */
	tmp = PP2C_CIBGMN \| PP2C_CIBGMX \| PP2C_CIBGN \| PP2C_CINMP;		writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
	writel(tmp, mmio + AHCI_VEND_PP2C);

	/* Phy Control OOB timing parameters COMWAKE */		/* Phy Control OOB timing parameters COMWAKE */
	tmp = PP3C_CWBGMN \| PP3C_CWBGMX \| PP3C_CWBGN \| PP3C_CWNMP;		writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
	writel(tmp, mmio + AHCI_VEND_PP3C);

	/* Phy Control Burst timing setting */		/* Phy Control Burst timing setting */
	tmp = PP4C_BMX \| PP4C_BNM \| PP4C_SFD \| PP4C_PTST;		writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
	writel(tmp, mmio + AHCI_VEND_PP4C);

	/* Rate Change Timer and Retry Interval Timer setting */		/* Rate Change Timer and Retry Interval Timer setting */
	tmp = PP5C_RIT \| PP5C_RCT;		writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
	writel(tmp, mmio + AHCI_VEND_PP5C);

	/* Rx Watermark setting */		/* Rx Watermark setting */
	tmp = PTC_RX_WM_VAL \| PTC_RSVD;		tmp = rx_watermark \| PTC_RSVD;
	writel(tmp, mmio + AHCI_VEND_PTC);		writel(tmp, mmio + AHCI_VEND_PTC);

	/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */		/* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
	tmp = PORT_SCTL_SPD_GEN2 \| PORT_SCTL_IPM;		tmp = PORT_SCTL_SPD_GEN3 \| PORT_SCTL_IPM;
	if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)		if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
	tmp = PORT_SCTL_SPD_GEN1 \| PORT_SCTL_IPM;		tmp = PORT_SCTL_SPD_GEN1 \| PORT_SCTL_IPM;
	writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);		writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
	@@ -168,6 +204,7 @@ static int ceva_ahci_probe(struct platform_device *pdev)
	struct device *dev = &pdev->dev;		struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;		struct ahci_host_priv *hpriv;
	struct ceva_ahci_priv *cevapriv;		struct ceva_ahci_priv *cevapriv;
			enum dev_dma_attr attr;
	int rc;		int rc;

	cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);		cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
	@@ -187,6 +224,65 @@ static int ceva_ahci_probe(struct platform_device *pdev)
	if (of_property_read_bool(np, "ceva,broken-gen2"))		if (of_property_read_bool(np, "ceva,broken-gen2"))
	cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;		cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;

			/* Read OOB timing value for COMINIT from device-tree */
			if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
			(u8 *)&cevapriv->pp2c[0], 4) < 0) {
			dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
			return -EINVAL;
			}

			if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
			(u8 *)&cevapriv->pp2c[1], 4) < 0) {
			dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
			return -EINVAL;
			}

			/* Read OOB timing value for COMWAKE from device-tree*/
			if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
			(u8 *)&cevapriv->pp3c[0], 4) < 0) {
			dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
			return -EINVAL;
			}

			if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
			(u8 *)&cevapriv->pp3c[1], 4) < 0) {
			dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
			return -EINVAL;
			}

			/* Read phy BURST timing value from device-tree */
			if (of_property_read_u8_array(np, "ceva,p0-burst-params",
			(u8 *)&cevapriv->pp4c[0], 4) < 0) {
			dev_warn(dev, "ceva,p0-burst-params property not defined\n");
			return -EINVAL;
			}

			if (of_property_read_u8_array(np, "ceva,p1-burst-params",
			(u8 *)&cevapriv->pp4c[1], 4) < 0) {
			dev_warn(dev, "ceva,p1-burst-params property not defined\n");
			return -EINVAL;
			}

			/* Read phy RETRY interval timing value from device-tree */
			if (of_property_read_u16_array(np, "ceva,p0-retry-params",
			(u16 *)&cevapriv->pp5c[0], 2) < 0) {
			dev_warn(dev, "ceva,p0-retry-params property not defined\n");
			return -EINVAL;
			}

			if (of_property_read_u16_array(np, "ceva,p1-retry-params",
			(u16 *)&cevapriv->pp5c[1], 2) < 0) {
			dev_warn(dev, "ceva,p1-retry-params property not defined\n");
			return -EINVAL;
			}

			/*
			* Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned
			* if CCI is enabled, so check for DEV_DMA_COHERENT.
			*/
			attr = device_get_dma_attr(dev);
			cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT);

	hpriv->plat_data = cevapriv;		hpriv->plat_data = cevapriv;

	/* CEVA specific initialization */		/* CEVA specific initialization */
	@@ -206,12 +302,37 @@ static int ceva_ahci_probe(struct platform_device *pdev)

	static int __maybe_unused ceva_ahci_suspend(struct device *dev)		static int __maybe_unused ceva_ahci_suspend(struct device *dev)
	{		{
	return ahci_platform_suspend_host(dev);		return ahci_platform_suspend(dev);
	}		}

	static int __maybe_unused ceva_ahci_resume(struct device *dev)		static int __maybe_unused ceva_ahci_resume(struct device *dev)
	{		{
	return ahci_platform_resume_host(dev);		struct ata_host *host = dev_get_drvdata(dev);
			struct ahci_host_priv *hpriv = host->private_data;
			int rc;

			rc = ahci_platform_enable_resources(hpriv);
			if (rc)
			return rc;

			/* Configure CEVA specific config before resuming HBA */
			ahci_ceva_setup(hpriv);

			rc = ahci_platform_resume_host(dev);
			if (rc)
			goto disable_resources;

			/* We resumed so update PM runtime state */
			pm_runtime_disable(dev);
			pm_runtime_set_active(dev);
			pm_runtime_enable(dev);

			return 0;

			disable_resources:
			ahci_platform_disable_resources(hpriv);

			return rc;
	}		}

	static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);		static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);

drivers/ata/ahci_imx.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -230,7 +230,7 @@ static int read_adc_sum(void dev, u16 rtune_ctl_reg, void __iomem mmio)
	{		{
	u16 adc_out_reg, read_sum;		u16 adc_out_reg, read_sum;
	u32 index, read_attempt;		u32 index, read_attempt;
	const u32 attempt_limit = 100;		const u32 attempt_limit = 200;

	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);		imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
	imx_phy_reg_write(rtune_ctl_reg, mmio);		imx_phy_reg_write(rtune_ctl_reg, mmio);

drivers/ata/libahci_platform.c

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -295,6 +295,7 @@ static int ahci_platform_get_phy(struct ahci_host_priv *hpriv, u32 port,
	node->name);		node->name);
	break;		break;
	}		}
			/* fall through */
	case -ENODEV:		case -ENODEV:
	/* continue normally */		/* continue normally */
	hpriv->phys[port] = NULL;		hpriv->phys[port] = NULL;