Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1a9c3d68 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "Resurrect Alchemy platforms by invoking the WAIT instructions with
  interrupts enabled.  This still leaves the race condition between
  testing TIF_NEED_RESCHED and the WAIT instruction for Alchemy
  platforms which need a different fix than other MIPS platforms.  But
  at least it gets MIPS platforms flying again.

  There are also fixes for two build errors (CONFIG_FTRACE=y with
  CONFIG_DYNAMIC_FTRACE=n) and CONFIG_VIRTUALIZATION without CONFIG_KVM"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: ftrace: Add missing CONFIG_DYNAMIC_FTRACE
  MIPS: include: mmu_context.h: Replace VIRTUALIZATION with KVM
  MIPS: Alchemy: fix wait function
parents 6673de0e cb2f9938

arch/mips/include/asm/mmu_context.h

+1 −1
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 
	if (! ((asid += ASID_INC) & ASID_MASK) ) {

		if (cpu_has_vtag_icache)

			flush_icache_all();

#ifdef CONFIG_VIRTUALIZATION

#ifdef CONFIG_KVM

		kvm_local_flush_tlb_all();      /* start new asid cycle */

#else

		local_flush_tlb_all();	/* start new asid cycle */

arch/mips/kernel/ftrace.c

+4 −0
Original line number Diff line number Diff line
@@ -25,12 +25,16 @@ 
#define MCOUNT_OFFSET_INSNS 4

#endif



#ifdef CONFIG_DYNAMIC_FTRACE



/* Arch override because MIPS doesn't need to run this from stop_machine() */

void arch_ftrace_update_code(int command)

{

	ftrace_modify_all_code(command);

}



#endif



/*

 * Check if the address is in kernel space

 *

arch/mips/kernel/idle.c

+7 −6
Original line number Diff line number Diff line
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void) 
}



/*

 * The Au1xxx wait is available only if using 32khz counter or

 * external timer source, but specifically not CP0 Counter.

 * alchemy/common/time.c may override cpu_wait!

 * Au1 'wait' is only useful when the 32kHz counter is used as timer,

 * since coreclock (and the cp0 counter) stops upon executing it. Only an

 * interrupt can wake it, so they must be enabled before entering idle modes.

 */

static void au1k_wait(void)

{

	unsigned long c0status = read_c0_status() | 1;	/* irqs on */



	__asm__(

	"	.set	mips3			\n"

	"	cache	0x14, 0(%0)		\n"

	"	cache	0x14, 32(%0)		\n"

	"	sync				\n"

	"	nop				\n"

	"	mtc0	%1, $12			\n" /* wr c0status */

	"	wait				\n"

	"	nop				\n"

	"	nop				\n"

	"	nop				\n"

	"	nop				\n"

	"	.set	mips0			\n"

	: : "r" (au1k_wait));

	local_irq_enable();

	: : "r" (au1k_wait), "r" (c0status));

}



static int __initdata nowait;