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Commit 1a4baafa authored by Will Deacon's avatar Will Deacon
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ARM: proc-*.S: place cpu_reset functions into .idmap.text section 



The CPU reset functions disable the MMU and therefore must be executed
with an identity mapping in place.

This patch places the CPU reset functions into the .idmap.text section,
causing the idmap code to include them as part of the identity mapping.

Acked-by: default avatarDave Martin <dave.martin@linaro.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent e6eadc67

arch/arm/mm/proc-arm1020.S

+3 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ ENTRY(cpu_arm1020_proc_fin) 
 * loc: location to jump to for soft reset

 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1020_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
@@ -107,6 +108,8 @@ ENTRY(cpu_arm1020_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	mov	pc, r0

ENDPROC(cpu_arm1020_reset)

	.popsection



/*

 * cpu_arm1020_do_idle()

arch/arm/mm/proc-arm1020e.S

+3 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ ENTRY(cpu_arm1020e_proc_fin) 
 * loc: location to jump to for soft reset

 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1020e_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
@@ -107,6 +108,8 @@ ENTRY(cpu_arm1020e_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	mov	pc, r0

ENDPROC(cpu_arm1020e_reset)

	.popsection



/*

 * cpu_arm1020e_do_idle()

arch/arm/mm/proc-arm1022.S

+3 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ ENTRY(cpu_arm1022_proc_fin) 
 * loc: location to jump to for soft reset

 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1022_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
@@ -96,6 +97,8 @@ ENTRY(cpu_arm1022_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	mov	pc, r0

ENDPROC(cpu_arm1022_reset)

	.popsection



/*

 * cpu_arm1022_do_idle()

arch/arm/mm/proc-arm1026.S

+3 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ ENTRY(cpu_arm1026_proc_fin) 
 * loc: location to jump to for soft reset

 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1026_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
@@ -96,6 +97,8 @@ ENTRY(cpu_arm1026_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	mov	pc, r0

ENDPROC(cpu_arm1026_reset)

	.popsection



/*

 * cpu_arm1026_do_idle()

arch/arm/mm/proc-arm6_7.S

+4 −0
Original line number Diff line number Diff line
@@ -225,6 +225,7 @@ ENTRY(cpu_arm7_set_pte_ext) 
 * Params  : r0 = address to jump to

 * Notes   : This sets up everything for a reset

 */

		.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm6_reset)

ENTRY(cpu_arm7_reset)

		mov	r1, #0
@@ -235,6 +236,9 @@ ENTRY(cpu_arm7_reset) 
		mov	r1, #0x30

		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc

		mov	pc, r0

ENDPROC(cpu_arm6_reset)

ENDPROC(cpu_arm7_reset)

		.popsection



		__CPUINIT