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Commit 1a2f7789 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm/keys: Move pte bits to correct headers 



Memory keys are supported only with hash translation mode. Instead of
using #ifdef in generic code move the key related pte bits to
respective headers

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 16b19f1a

arch/powerpc/include/asm/book3s/64/hash-4k.h

+8 −0
Original line number Diff line number Diff line
@@ -34,6 +34,14 @@ 
#define H_PAGE_COMBO	0x0

#define H_PTE_FRAG_NR	0

#define H_PTE_FRAG_SIZE_SHIFT  0



/* memory key bits, only 8 keys supported */

#define H_PTE_PKEY_BIT0	0

#define H_PTE_PKEY_BIT1	0

#define H_PTE_PKEY_BIT2	_RPAGE_RSV3

#define H_PTE_PKEY_BIT3	_RPAGE_RSV4

#define H_PTE_PKEY_BIT4	_RPAGE_RSV5



/*

 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()

 */

arch/powerpc/include/asm/book3s/64/hash-64k.h

+7 −0
Original line number Diff line number Diff line
@@ -16,6 +16,13 @@ 
#define H_PAGE_BUSY	_RPAGE_RPN44     /* software: PTE & hash are busy */

#define H_PAGE_HASHPTE	_RPAGE_RPN43	/* PTE has associated HPTE */



/* memory key bits. */

#define H_PTE_PKEY_BIT0	_RPAGE_RSV1

#define H_PTE_PKEY_BIT1	_RPAGE_RSV2

#define H_PTE_PKEY_BIT2	_RPAGE_RSV3

#define H_PTE_PKEY_BIT3	_RPAGE_RSV4

#define H_PTE_PKEY_BIT4	_RPAGE_RSV5



/*

 * We need to differentiate between explicit huge page and THP huge

 * page, since THP huge page also need to track real subpage details

arch/powerpc/include/asm/book3s/64/pgtable.h

+0 −19
Original line number Diff line number Diff line
@@ -60,25 +60,6 @@ 
/* Max physical address bit as per radix table */

#define _RPAGE_PA_MAX		57



#ifdef CONFIG_PPC_MEM_KEYS

#ifdef CONFIG_PPC_64K_PAGES

#define H_PTE_PKEY_BIT0	_RPAGE_RSV1

#define H_PTE_PKEY_BIT1	_RPAGE_RSV2

#else /* CONFIG_PPC_64K_PAGES */

#define H_PTE_PKEY_BIT0	0 /* _RPAGE_RSV1 is not available */

#define H_PTE_PKEY_BIT1	0 /* _RPAGE_RSV2 is not available */

#endif /* CONFIG_PPC_64K_PAGES */

#define H_PTE_PKEY_BIT2	_RPAGE_RSV3

#define H_PTE_PKEY_BIT3	_RPAGE_RSV4

#define H_PTE_PKEY_BIT4	_RPAGE_RSV5

#else /*  CONFIG_PPC_MEM_KEYS */

#define H_PTE_PKEY_BIT0	0

#define H_PTE_PKEY_BIT1	0

#define H_PTE_PKEY_BIT2	0

#define H_PTE_PKEY_BIT3	0

#define H_PTE_PKEY_BIT4	0

#endif /*  CONFIG_PPC_MEM_KEYS */



/*

 * Max physical address bit we will use for now.

 *