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Commit 19c0389b authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Add BroadwellX V10 event file 



Add a Intel event file for perf.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-min8rez83cab2zrb9i3dlkx5@git.kernel.org


[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent b74d1315

tools/perf/pmu-events/arch/x86/broadwellx/cache.json

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tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json

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[

    {

        "EventCode": "0xC1",

        "UMask": "0x8",

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "Errata": "BDM30",

        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC1",

        "UMask": "0x10",

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "Errata": "BDM30",

        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x1",

        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "PEBS": "1",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x2",

        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "PEBS": "1",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x4",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "PEBS": "1",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x8",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "PEBS": "1",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x10",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "PEBS": "1",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x2",

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x4",

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.X87_INPUT",

        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x8",

        "BriefDescription": "Number of SIMD FP assists due to Output values",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x10",

        "BriefDescription": "Number of SIMD FP assists due to input values",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xCA",

        "UMask": "0x1e",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "EventName": "FP_ASSIST.ANY",

        "CounterMask": "1",

        "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "SampleAfterValue": "100003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xc7",

        "UMask": "0x20",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "PEBS": "1",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x3",

        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x3c",

        "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.PACKED",

        "SampleAfterValue": "2000004",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x2a",

        "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.SINGLE",

        "SampleAfterValue": "2000005",

        "CounterHTOff": "0,1,2,3"

    },

    {

        "EventCode": "0xC7",

        "UMask": "0x15",

        "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?.",

        "Counter": "0,1,2,3",

        "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",

        "SampleAfterValue": "2000006",

        "CounterHTOff": "0,1,2,3"

    }

]
 
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tools/perf/pmu-events/arch/x86/broadwellx/frontend.json

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tools/perf/pmu-events/arch/x86/broadwellx/memory.json

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tools/perf/pmu-events/arch/x86/broadwellx/other.json

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[

    {

        "EventCode": "0x5C",

        "UMask": "0x1",

        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",

        "Counter": "0,1,2,3",

        "EventName": "CPL_CYCLES.RING0",

        "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x5C",

        "UMask": "0x2",

        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",

        "Counter": "0,1,2,3",

        "EventName": "CPL_CYCLES.RING123",

        "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EdgeDetect": "1",

        "EventCode": "0x5C",

        "UMask": "0x1",

        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",

        "Counter": "0,1,2,3",

        "EventName": "CPL_CYCLES.RING0_TRANS",

        "CounterMask": "1",

        "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",

        "SampleAfterValue": "100007",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0x63",

        "UMask": "0x1",

        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",

        "Counter": "0,1,2,3",

        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",

        "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",

        "SampleAfterValue": "2000003",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

]
 
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