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Commit 19bc4981 authored by Robert Hodaszi's avatar Robert Hodaszi Committed by Jonathan Cameron
Browse files

iio: mxs-lradc: fix divider 



All channels' single measurement are happening on CH 0. So enabling / disabling
the divider once is not enough, because it has impact on all channels.

Set only a flag, then check this on each measurement, and enable / disable the
divider as required.

Signed-off-by: default avatarRobert Hodaszi <robert.hodaszi@digi.com>
Cc: Stable@vger.kernel.org
Acked-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
parent 8ba42fb7

drivers/staging/iio/adc/mxs-lradc.c

+8 −4
Original line number Original line Diff line number Diff line
@@ -846,6 +846,14 @@ static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val) 
			LRADC_CTRL1);

			LRADC_CTRL1);

	mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);

	mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);





	/* Enable / disable the divider per requirement */

	if (test_bit(chan, &lradc->is_divided))

		mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,

			LRADC_CTRL2);

	else

		mxs_lradc_reg_clear(lradc,

			1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);



	/* Clean the slot's previous content, then set new one. */

	/* Clean the slot's previous content, then set new one. */

	mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),

	mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),

			LRADC_CTRL4);

			LRADC_CTRL4);
@@ -961,15 +969,11 @@ static int mxs_lradc_write_raw(struct iio_dev *iio_dev, 
		if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&

		if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&

		    val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {

		    val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {

			/* divider by two disabled */

			/* divider by two disabled */

			writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,

			       lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);

			clear_bit(chan->channel, &lradc->is_divided);

			clear_bit(chan->channel, &lradc->is_divided);

			ret = 0;

			ret = 0;

		} else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&

		} else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&

			   val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {

			   val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {

			/* divider by two enabled */

			/* divider by two enabled */

			writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,

			       lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);

			set_bit(chan->channel, &lradc->is_divided);

			set_bit(chan->channel, &lradc->is_divided);

			ret = 0;

			ret = 0;

		}

		}