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Commit 19971c0b authored by James Hogan's avatar James Hogan Committed by Ralf Baechle
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MIPS: cevt-r4k: Move handle_perf_irq() out of header 



Long ago, commit 8531a35e ("[MIPS] SMTC: Fix SMTC dyntick support.")
moved handle_perf_irq() out of cevt-r4k.c into a header so it could be
shared with cevt-smtc.c.

Slightly less long ago, commit b633648c ("MIPS: MT: Remove SMTC
support") removed all traces of SMTC support, including cevt-smtc.c,
leaving cevt-r4k.c once again the sole user of handle_perf_irq(),
therefore move it back into cevt-r4k.c from the header.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9123/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c9d6c8b0

arch/mips/include/asm/cevt-r4k.h

+0 −19
Original line number Diff line number Diff line
@@ -27,23 +27,4 @@ irqreturn_t c0_compare_interrupt(int, void *); 
extern struct irqaction c0_compare_irqaction;

extern int cp0_timer_irq_installed;



/*

 * Possibly handle a performance counter interrupt.

 * Return true if the timer interrupt should not be checked

 */



static inline int handle_perf_irq(int r2)

{

	/*

	 * The performance counter overflow interrupt may be shared with the

	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a

	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)

	 * and we can't reliably determine if a counter interrupt has also

	 * happened (!r2) then don't check for a timer interrupt.

	 */

	return (cp0_perfcount_irq < 0) &&

		perf_irq() == IRQ_HANDLED &&

		!r2;

}



#endif /* __ASM_CEVT_R4K_H */

arch/mips/kernel/cevt-r4k.c

+18 −0
Original line number Diff line number Diff line
@@ -37,6 +37,24 @@ void mips_set_clock_mode(enum clock_event_mode mode, 
DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);

int cp0_timer_irq_installed;



/*

 * Possibly handle a performance counter interrupt.

 * Return true if the timer interrupt should not be checked

 */

static inline int handle_perf_irq(int r2)

{

	/*

	 * The performance counter overflow interrupt may be shared with the

	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a

	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)

	 * and we can't reliably determine if a counter interrupt has also

	 * happened (!r2) then don't check for a timer interrupt.

	 */

	return (cp0_perfcount_irq < 0) &&

		perf_irq() == IRQ_HANDLED &&

		!r2;

}



irqreturn_t c0_compare_interrupt(int irq, void *dev_id)

{

	const int r2 = cpu_has_mips_r2_r6;