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Commit 193fb3c1 authored by mar.krzeminski's avatar mar.krzeminski Committed by Cyrille Pitchen
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mtd: spi-nor: Disable chip erase for Micron n25q00. 



Micron n25q00 are stacked chips, thus do not support chip erase.
>From now spi-nor framework will not send chip erase command,
instead will use sector at time erase procedure.

Signed-off-by: default avatarMarcin Krzeminski <mar.krzeminski@gmail.com>
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
parent 2f5ad7f0

drivers/mtd/spi-nor/spi-nor.c

+2 −2
Original line number Diff line number Diff line
@@ -1036,8 +1036,8 @@ static const struct flash_info spi_nor_ids[] = { 
	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },

	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },

	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },

	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },

	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },

	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },

	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },



	/* PMC */

	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },