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Unverified Commit 18ba210a authored by Matt Redfearn's avatar Matt Redfearn Committed by James Hogan
Browse files

MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV 



Remove the need to check that __mips_isa_rev is defined by using the
newly added MIPS_ISA_REV.

Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: "Maciej W. Rozycki" <macro@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18675/


Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
parent 16909052

arch/mips/include/asm/cpu-features.h

+3 −2
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 


#include <asm/cpu.h>

#include <asm/cpu-info.h>

#include <asm/isa-rev.h>

#include <cpu-feature-overrides.h>



/*
@@ -493,7 +494,7 @@ 
# define cpu_has_perf		(cpu_data[0].options & MIPS_CPU_PERF)

#endif



#if defined(CONFIG_SMP) && defined(__mips_isa_rev) && (__mips_isa_rev >= 6)

#if defined(CONFIG_SMP) && (MIPS_ISA_REV >= 6)

/*

 * Some systems share FTLB RAMs between threads within a core (siblings in

 * kernel parlance). This means that FTLB entries may become invalid at almost
@@ -525,7 +526,7 @@ 
#  define cpu_has_shared_ftlb_entries \

	(current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)

# endif

#endif /* SMP && __mips_isa_rev >= 6 */

#endif /* SMP && MIPS_ISA_REV >= 6 */



#ifndef cpu_has_shared_ftlb_ram

# define cpu_has_shared_ftlb_ram 0