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Commit 18afea04 authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Russell King
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[ARM] 3294/1: don't invalidate individual BTB entries on ARMv6 



Patch from Nicolas Pitre

Doing so adds a much larger cost to the loop than the cost implied by
simply invalidating the whole BTB at once.

Signed-off-by: default avatarNicolas Pitre <nico@cam.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 8a052e0b

arch/arm/mm/cache-v6.S

+6 −12
Original line number Diff line number Diff line
@@ -92,22 +92,16 @@ ENTRY(v6_coherent_kern_range) 
 *	- the Icache does not read data from the write buffer

 */

ENTRY(v6_coherent_user_range)

	bic	r0, r0, #CACHE_LINE_SIZE - 1

1:



#ifdef HARVARD_CACHE

	mcr	p15, 0, r0, c7, c10, 1		@ clean D line

	bic	r0, r0, #CACHE_LINE_SIZE - 1

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D line

	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I line

#endif

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #BTB_FLUSH_SIZE

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #BTB_FLUSH_SIZE

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #BTB_FLUSH_SIZE

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #BTB_FLUSH_SIZE

	add	r0, r0, #CACHE_LINE_SIZE

	cmp	r0, r1

	blo	1b

#endif

	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB

#ifdef HARVARD_CACHE

	mov	r0, #0

	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer