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Commit 18ad01ef authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: enable SRBM timeout interrupt on SI 



Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dc12a3ec

drivers/gpu/drm/radeon/si.c

+7 −0
Original line number Diff line number Diff line
@@ -3162,6 +3162,8 @@ static void si_gpu_init(struct radeon_device *rdev) 
	}



	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

	WREG32(SRBM_INT_CNTL, 1);

	WREG32(SRBM_INT_ACK, 1);



	evergreen_fix_pci_max_read_req_size(rdev);
@@ -5911,6 +5913,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev) 
	tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

	WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);

	WREG32(GRBM_INT_CNTL, 0);

	WREG32(SRBM_INT_CNTL, 0);

	if (rdev->num_crtc >= 2) {

		WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

		WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -6610,6 +6613,10 @@ int si_irq_process(struct radeon_device *rdev) 
				break;

			}

			break;

		case 96:

			DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));

			WREG32(SRBM_INT_ACK, 0x1);

			break;

		case 124: /* UVD */

			DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);

			radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);

drivers/gpu/drm/radeon/sid.h

+4 −0
Original line number Diff line number Diff line
@@ -358,6 +358,10 @@ 
#define	CC_SYS_RB_BACKEND_DISABLE			0xe80

#define	GC_USER_SYS_RB_BACKEND_DISABLE			0xe84



#define SRBM_READ_ERROR					0xE98

#define SRBM_INT_CNTL					0xEA0

#define SRBM_INT_ACK					0xEA8



#define	SRBM_STATUS2				        0x0EC4

#define		DMA_BUSY 				(1 << 5)

#define		DMA1_BUSY 				(1 << 6)