Commit 18022894 authored Sep 01, 2016 by James Hogan Committed by Ralf Baechle Oct 04, 2016

MIPS: traps: 64bit kernels should read CP0_EBase 64bit



When reading the CP0_EBase register containing the WG (write gate) bit,
the ebase variable should be set to the full value of the register, i.e.
on a 64-bit kernel the full 64-bit width of the register via
read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width
including bits 31:30 which may be writeable.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14148/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 72bc8c75

arch/mips/kernel/traps.c

+11 −2

Original line number	Diff line number	Diff line
		@@ -2215,9 +2215,18 @@ void __init trap_init(void)
		} else {
		ebase = CAC_BASE;

		if (cpu_has_mips_r2_r6)
		if (cpu_has_mips_r2_r6) {
		if (cpu_has_ebase_wg) {
		#ifdef CONFIG_64BIT
		ebase = (read_c0_ebase_64() & ~0xfff);
		#else
		ebase = (read_c0_ebase() & ~0xfff);
		#endif
		} else {
		ebase += (read_c0_ebase() & 0x3ffff000);
		}
		}
		}

		if (cpu_has_mmips) {
		unsigned int config3 = read_c0_config3();