Commit 17c99d94 authored Mar 16, 2017 by Huacai Chen Committed by Ralf Baechle Apr 10, 2017

MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15755/

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 294d6274

arch/mips/Kconfig

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1374,6 +1374,7 @@ config CPU_LOONGSON3
	select WEAK_ORDERING		select WEAK_ORDERING
	select WEAK_REORDERING_BEYOND_LLSC		select WEAK_REORDERING_BEYOND_LLSC
	select MIPS_PGD_C0_CONTEXT		select MIPS_PGD_C0_CONTEXT
			select MIPS_L1_CACHE_SHIFT_6
	select GPIOLIB		select GPIOLIB
	help		help
	The Loongson 3 processor implements the MIPS64R2 instruction		The Loongson 3 processor implements the MIPS64R2 instruction