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Commit 17a00cf7 authored by Matthew Auld's avatar Matthew Auld Committed by Chris Wilson
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drm/i915: support 64K pages for the 48b PPGTT 



Support inserting 64K pages into the 48b PPGTT.

v2: check for 64K scratch

v3: we should only have to re-adjust maybe_64K at every sg interval

Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-15-matthew.auld@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-14-chris@chris-wilson.co.uk
parent aa095871

drivers/gpu/drm/i915/i915_gem_gtt.c

+31 −0
Original line number Diff line number Diff line
@@ -1069,6 +1069,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, 
		struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];

		struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];

		unsigned int page_size;

		bool maybe_64K = false;

		gen8_pte_t encode = pte_encode;

		gen8_pte_t *vaddr;

		u16 index, max;
@@ -1090,6 +1091,13 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, 
			max = GEN8_PTES;

			page_size = I915_GTT_PAGE_SIZE;



			if (!index &&

			    vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&

			    IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&

			    (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||

			     rem >= (max - index) << PAGE_SHIFT))

				maybe_64K = true;



			vaddr = kmap_atomic_px(pt);

		}
@@ -1109,12 +1117,35 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, 
				iter->dma = sg_dma_address(iter->sg);

				iter->max = iter->dma + rem;



				if (maybe_64K && index < max &&

				    !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&

				      (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||

				       rem >= (max - index) << PAGE_SHIFT)))

					maybe_64K = false;



				if (unlikely(!IS_ALIGNED(iter->dma, page_size)))

					break;

			}

		} while (rem >= page_size && index < max);



		kunmap_atomic(vaddr);



		/*

		 * Is it safe to mark the 2M block as 64K? -- Either we have

		 * filled whole page-table with 64K entries, or filled part of

		 * it and have reached the end of the sg table and we have

		 * enough padding.

		 */

		if (maybe_64K &&

		    (index == max ||

		     (i915_vm_has_scratch_64K(vma->vm) &&

		      !iter->sg && IS_ALIGNED(vma->node.start +

					      vma->node.size,

					      I915_GTT_PAGE_SIZE_2M)))) {

			vaddr = kmap_atomic_px(pd);

			vaddr[idx.pde] |= GEN8_PDE_IPS_64K;

			kunmap_atomic(vaddr);

		}

	} while (iter->sg);

}

drivers/gpu/drm/i915/i915_gem_gtt.h

+7 −0
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ typedef u64 gen8_ppgtt_pml4e_t; 
#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))

#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))



#define GEN8_PDE_IPS_64K BIT(11)

#define GEN8_PDE_PS_2M   BIT(7)



struct sg_table;
@@ -352,6 +353,12 @@ i915_vm_is_48bit(const struct i915_address_space *vm) 
	return (vm->total - 1) >> 32;

}



static inline bool

i915_vm_has_scratch_64K(struct i915_address_space *vm)

{

	return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K);

}



/* The Graphics Translation Table is the way in which GEN hardware translates a

 * Graphics Virtual Address into a Physical Address. In addition to the normal

 * collateral associated with any va->pa translations GEN hardware also has a