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Commit 166869b3 authored by Madhav Chauhan's avatar Madhav Chauhan Committed by Jani Nikula
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drm/i915/icl: Define PORT_CL_DW_10 register 



This register used to power down individual lanes for
DDI/DSI ports. Bitfields to power up/down various
combinations of lanes are also added in this patch.

v2: Review comments from Jani N
    - Use override instead of "override" for bitfields
    - Define mask for override bitfield
    - Define PWR_DOWN_LN* macros shifted in place
v3: Correct PWR_DOWN_LN_MASK value (Jani N)

Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530798591-2077-6-git-send-email-madhav.chauhan@intel.com
parent b1cb21a5

drivers/gpu/drm/i915/i915_reg.h

+20 −0
Original line number Diff line number Diff line
@@ -1720,6 +1720,26 @@ enum i915_power_well_id { 
#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \

						 _ICL_PORT_CL_DW5_B)



#define _CNL_PORT_CL_DW10_A		0x162028

#define _ICL_PORT_CL_DW10_B		0x6c028

#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\

						   _CNL_PORT_CL_DW10_A, \

						   _ICL_PORT_CL_DW10_B)

#define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)

#define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25

#define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)

#define  PWR_UP_ALL_LANES		(0x0 << 4)

#define  PWR_DOWN_LN_3_2_1		(0xe << 4)

#define  PWR_DOWN_LN_3_2		(0xc << 4)

#define  PWR_DOWN_LN_3			(0x8 << 4)

#define  PWR_DOWN_LN_2_1_0		(0x7 << 4)

#define  PWR_DOWN_LN_1_0		(0x3 << 4)

#define  PWR_DOWN_LN_1			(0x2 << 4)

#define  PWR_DOWN_LN_3_1		(0xa << 4)

#define  PWR_DOWN_LN_3_1_0		(0xb << 4)

#define  PWR_DOWN_LN_MASK		(0xf << 4)

#define  PWR_DOWN_LN_SHIFT		4



#define _PORT_CL1CM_DW9_A		0x162024

#define _PORT_CL1CM_DW9_BC		0x6C024

#define   IREF0RC_OFFSET_SHIFT		8