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Commit 15da0950 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-armada-devel' of git://git.armlinux.org.uk/~rmk/linux-arm into drm-next 



This set of changes migrates Armada DRM from legacy modeset to atomic
modeset.  This is everything from the "Transition Armada DRM planes to
atomic state" and "Finish Armada DRM transition to atomic modeset"
patch sets as posted on drm-devel, excluding the "Finish Armada DRM DT
support" series.

These series did not evoke any comments - if there are any, these can
be addressed via follow up patches.

Developed and tested on Dove Cubox with xf86-video-armada including the
overlay plane, and also tested with the tools in libdrm.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180730110543.GA30664@rmk-PC.armlinux.org.uk
parents f8f15c34 aa595c00

drivers/gpu/drm/armada/Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

armada-y	:= armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \

		   armada_gem.o armada_overlay.o armada_trace.o

		   armada_gem.o armada_overlay.o armada_plane.o armada_trace.o

armada-y	+= armada_510.o

armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o

drivers/gpu/drm/armada/armada_510.c

+23 −1
Original line number Diff line number Diff line
@@ -27,6 +27,10 @@ static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev) 
	/* Lower the watermark so to eliminate jitter at higher bandwidths */

	armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);



	/* Initialise SPU register */

	writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,

		       dcrtc->base + LCD_SPU_ADV_REG);



	return 0;

}
@@ -75,9 +79,27 @@ static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc, 
	return 0;

}



static void armada510_crtc_disable(struct armada_crtc *dcrtc)

{

	if (!IS_ERR(dcrtc->clk)) {

		clk_disable_unprepare(dcrtc->clk);

		dcrtc->clk = ERR_PTR(-EINVAL);

	}

}



static void armada510_crtc_enable(struct armada_crtc *dcrtc,

	const struct drm_display_mode *mode)

{

	if (IS_ERR(dcrtc->clk)) {

		dcrtc->clk = dcrtc->extclk[0];

		WARN_ON(clk_prepare_enable(dcrtc->clk));

	}

}



const struct armada_variant armada510_ops = {

	.has_spu_adv_reg = true,

	.spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,

	.init = armada510_crtc_init,

	.compute_clock = armada510_crtc_compute_clock,

	.disable = armada510_crtc_disable,

	.enable = armada510_crtc_enable,

};