Loading arch/arm/boot/dts/berlin2q.dtsi +13 −12 Original line number Diff line number Diff line Loading @@ -62,6 +62,19 @@ }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; Loading @@ -76,18 +89,6 @@ ranges = <0 0xf7000000 0x1000000>; interrupt-parent = <&gic>; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; Loading Loading
arch/arm/boot/dts/berlin2q.dtsi +13 −12 Original line number Diff line number Diff line Loading @@ -62,6 +62,19 @@ }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; Loading @@ -76,18 +89,6 @@ ranges = <0 0xf7000000 0x1000000>; interrupt-parent = <&gic>; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; Loading