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Commit 155dfc7b authored by Peter De Schrijver's avatar Peter De Schrijver Committed by Thierry Reding
Browse files

soc/tegra: Add efuse and apbmisc bindings 



Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and
Tegra124.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 783c8f4c

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt

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+40 −0
Original line number Diff line number Diff line 
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.



Required properties:

- compatible : should be:

	"nvidia,tegra20-efuse"

	"nvidia,tegra30-efuse"

	"nvidia,tegra114-efuse"

	"nvidia,tegra124-efuse"

  Details:

  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data

	due to a hardware bug. Tegra20 also lacks certain information which is

	available in later generations such as fab code, lot code, wafer id,..

  nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:

	The differences between these SoCs are the size of the efuse array,

	the location of the spare (OEM programmable) bits and the location of

	the speedo data.

- reg: Should contain 1 entry: the entry gives the physical address and length

       of the fuse registers.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - fuse

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

 - fuse



Example:



	fuse@7000f800 {

		compatible = "nvidia,tegra20-efuse";

		reg = <0x7000F800 0x400>,

		      <0x70000000 0x400>;

		clocks = <&tegra_car TEGRA20_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block



Required properties:

- compatible : should be:

       "nvidia,tegra20-apbmisc"

       "nvidia,tegra30-apbmisc"

       "nvidia,tegra114-apbmisc"

       "nvidia,tegra124-apbmisc"

- reg: Should contain 2 entries: the first entry gives the physical address

       and length of the registers which contain revision and debug features.

       The second entry gives the physical address and length of the

       registers indicating the strapping options.

arch/arm/boot/dts/tegra114.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -220,6 +220,12 @@ 
		interrupt-controller;

	};



	apbmisc@70000800 {

		compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64   /* Chip revision */

		       0x70000008 0x04>; /* Strapping options */

	};



	pinmux: pinmux@70000868 {

		compatible = "nvidia,tegra114-pinmux";

		reg = <0x70000868 0x148		/* Pad control registers */
@@ -485,6 +491,15 @@ 
		clock-names = "pclk", "clk32k_in";

	};



	fuse@7000f800 {

		compatible = "nvidia,tegra114-efuse";

		reg = <0x7000f800 0x400>;

		clocks = <&tegra_car TEGRA114_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};



	iommu@70019010 {

		compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";

		reg = <0x70019010 0x02c

arch/arm/boot/dts/tegra124.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -179,6 +179,12 @@ 
		#dma-cells = <1>;

	};



	apbmisc@0,70000800 {

		compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";

		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */

		      <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */

	};



	pinmux: pinmux@0,70000868 {

		compatible = "nvidia,tegra124-pinmux";

		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
@@ -449,6 +455,15 @@ 
		clock-names = "pclk", "clk32k_in";

	};



	fuse@0,7000f800 {

		compatible = "nvidia,tegra124-efuse";

		reg = <0x0 0x7000f800 0x0 0x400>;

		clocks = <&tegra_car TEGRA124_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};



	sdhci@0,700b0000 {

		compatible = "nvidia,tegra124-sdhci";

		reg = <0x0 0x700b0000 0x0 0x200>;

arch/arm/boot/dts/tegra20.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -236,6 +236,12 @@ 
		interrupt-controller;

	};



	apbmisc@70000800 {

		compatible = "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64   /* Chip revision */

		       0x70000008 0x04>; /* Strapping options */

	};



	pinmux: pinmux@70000014 {

		compatible = "nvidia,tegra20-pinmux";

		reg = <0x70000014 0x10   /* Tri-state registers */
@@ -545,6 +551,15 @@ 
		#size-cells = <0>;

	};



	fuse@7000f800 {

		compatible = "nvidia,tegra20-efuse";

		reg = <0x7000F800 0x400>;

		clocks = <&tegra_car TEGRA20_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};



	pcie-controller@80003000 {

		compatible = "nvidia,tegra20-pcie";

		device_type = "pci";