Loading arch/arm/include/asm/assembler.h +3 −7 Original line number Diff line number Diff line Loading @@ -246,18 +246,14 @@ * * This macro is intended for forcing the CPU into SVC mode at boot time. * you cannot return to the original mode. * * Beware, it also clobers LR. */ .macro safe_svcmode_maskall reg:req #if __LINUX_ARM_ARCH__ >= 6 mrs \reg , cpsr mov lr , \reg and lr , lr , #MODE_MASK cmp lr , #HYP_MODE orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT eor \reg, \reg, #HYP_MODE tst \reg, #MODE_MASK bic \reg , \reg , #MODE_MASK orr \reg , \reg , #SVC_MODE orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) bne 1f orr \reg, \reg, #PSR_A_BIT Loading arch/arm/include/asm/virt.h +2 −2 Original line number Diff line number Diff line Loading @@ -24,9 +24,9 @@ /* * Flag indicating that the kernel was not entered in the same mode on every * CPU. The zImage loader stashes this value in an SPSR, so we need an * architecturally defined flag bit here (the N flag, as it happens) * architecturally defined flag bit here. */ #define BOOT_CPU_MODE_MISMATCH (1<<31) #define BOOT_CPU_MODE_MISMATCH PSR_N_BIT #ifndef __ASSEMBLY__ Loading arch/arm/mm/Kconfig +3 −7 Original line number Diff line number Diff line Loading @@ -629,8 +629,9 @@ config ARM_THUMBEE make use of it. Say N for code that can run on CPUs without ThumbEE. config ARM_VIRT_EXT bool "Native support for the ARM Virtualization Extensions" depends on MMU && CPU_V7 bool depends on MMU default y if CPU_V7 help Enable the kernel to make use of the ARM Virtualization Extensions to install hypervisors without run-time firmware Loading @@ -640,11 +641,6 @@ config ARM_VIRT_EXT use of this feature. Refer to Documentation/arm/Booting for details. It is safe to enable this option even if the kernel may not be booted in HYP mode, may not have support for the virtualization extensions, or may be booted with a non-compliant bootloader. config SWP_EMULATE bool "Emulate SWP/SWPB instructions" depends on !CPU_USE_DOMAINS && CPU_V7 Loading Loading
arch/arm/include/asm/assembler.h +3 −7 Original line number Diff line number Diff line Loading @@ -246,18 +246,14 @@ * * This macro is intended for forcing the CPU into SVC mode at boot time. * you cannot return to the original mode. * * Beware, it also clobers LR. */ .macro safe_svcmode_maskall reg:req #if __LINUX_ARM_ARCH__ >= 6 mrs \reg , cpsr mov lr , \reg and lr , lr , #MODE_MASK cmp lr , #HYP_MODE orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT eor \reg, \reg, #HYP_MODE tst \reg, #MODE_MASK bic \reg , \reg , #MODE_MASK orr \reg , \reg , #SVC_MODE orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) bne 1f orr \reg, \reg, #PSR_A_BIT Loading
arch/arm/include/asm/virt.h +2 −2 Original line number Diff line number Diff line Loading @@ -24,9 +24,9 @@ /* * Flag indicating that the kernel was not entered in the same mode on every * CPU. The zImage loader stashes this value in an SPSR, so we need an * architecturally defined flag bit here (the N flag, as it happens) * architecturally defined flag bit here. */ #define BOOT_CPU_MODE_MISMATCH (1<<31) #define BOOT_CPU_MODE_MISMATCH PSR_N_BIT #ifndef __ASSEMBLY__ Loading
arch/arm/mm/Kconfig +3 −7 Original line number Diff line number Diff line Loading @@ -629,8 +629,9 @@ config ARM_THUMBEE make use of it. Say N for code that can run on CPUs without ThumbEE. config ARM_VIRT_EXT bool "Native support for the ARM Virtualization Extensions" depends on MMU && CPU_V7 bool depends on MMU default y if CPU_V7 help Enable the kernel to make use of the ARM Virtualization Extensions to install hypervisors without run-time firmware Loading @@ -640,11 +641,6 @@ config ARM_VIRT_EXT use of this feature. Refer to Documentation/arm/Booting for details. It is safe to enable this option even if the kernel may not be booted in HYP mode, may not have support for the virtualization extensions, or may be booted with a non-compliant bootloader. config SWP_EMULATE bool "Emulate SWP/SWPB instructions" depends on !CPU_USE_DOMAINS && CPU_V7 Loading