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Commit 14b5057a authored by Joel Stanley's avatar Joel Stanley Committed by Philipp Zabel
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dt-bindings: aspeed-lpc: Add reset controller 



This describes the reset controller present in the LPC address space.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
[p.zabel@pengutronix.de: removed a space before tab in indent]
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent 320da785

Documentation/devicetree/bindings/mfd/aspeed-lpc.txt

+21 −0
Original line number Diff line number Diff line
@@ -135,3 +135,24 @@ lhc: lhc@20 { 
	compatible = "aspeed,ast2500-lhc";

	reg = <0x20 0x24 0x48 0x8>;

};



LPC reset control

-----------------



The UARTs present in the ASPEED SoC can have their resets tied to the reset

state of the LPC bus. Some systems may chose to modify this configuration.



Required properties:



 - compatible:		"aspeed,ast2500-lpc-reset" or

			"aspeed,ast2400-lpc-reset"

 - reg:			offset and length of the IP in the LHC memory region

 - #reset-controller	indicates the number of reset cells expected



Example:



lpc_reset: reset-controller@18 {

        compatible = "aspeed,ast2500-lpc-reset";

        reg = <0x18 0x4>;

        #reset-cells = <1>;

};