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Commit 13888d78 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
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drm/i915: make the panel fitter work on pipes B and C on IVB 



I actually found this problem on Haswell, but then discovered Ivy
Bridge also has it by reading the spec.

I don't have the hardware to test this.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 79935fca

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -3339,6 +3339,8 @@ 
#define _PFA_CTL_1               0x68080

#define _PFB_CTL_1               0x68880

#define  PF_ENABLE              (1<<31)

#define  PF_PIPE_SEL_MASK_IVB	(3<<29)

#define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)

#define  PF_FILTER_MASK		(3<<23)

#define  PF_FILTER_PROGRAMMED	(0<<23)

#define  PF_FILTER_MED_3x3	(1<<23)

drivers/gpu/drm/i915/intel_display.c

+5 −1
Original line number Diff line number Diff line
@@ -3387,6 +3387,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
		 * as some pre-programmed values are broken,

		 * e.g. x201.

		 */

		if (IS_IVYBRIDGE(dev))

			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |

						 PF_PIPE_SEL_IVB(pipe));

		else

			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);

		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);

		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);