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Commit 12c0a0e8 authored by Julien CHAUVEAU's avatar Julien CHAUVEAU Committed by Heiko Stuebner
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clk: rockchip: fix rk3188 USB HSIC PHY clock divider 



The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).

Signed-off-by: default avatarJulien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent b7bdb7f4

drivers/clk/rockchip/clk-rk3188.c

+1 −1
Original line number Diff line number Diff line
@@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { 
			RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,

			RK2928_CLKGATE_CON(3), 6, GFLAGS),

	DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,

			RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),

			RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),



	MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,

			RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),