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Commit 12b2905a authored by Marc Zyngier's avatar Marc Zyngier
Browse files

irqchip/gic-v3-its: Honor hypervisor enforced LPI range 



A recent extension to the GIC architecture allows a hypervisor to
arbitrarily reduce the number of LPIs available to a guest, no
matter what the GIC says about the valid range of IntIDs.

Let's factor in this information when computing the number of
available LPIs

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent a4f9edb2

drivers/irqchip/irq-gic-v3-its.c

+9 −0
Original line number Diff line number Diff line
@@ -1541,8 +1541,17 @@ static int free_lpi_range(u32 base, u32 nr_lpis) 
static int __init its_lpi_init(u32 id_bits)

{

	u32 lpis = (1UL << id_bits) - 8192;

	u32 numlpis;

	int err;



	numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);



	if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {

		lpis = numlpis;

		pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",

			lpis);

	}



	/*

	 * Initializing the allocator is just the same as freeing the

	 * full range of LPIs.

include/linux/irqchip/arm-gic-v3.h

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#define GICD_TYPER_MBIS			(1U << 16)



#define GICD_TYPER_ID_BITS(typer)	((((typer) >> 19) & 0x1f) + 1)

#define GICD_TYPER_NUM_LPIS(typer)	((((typer) >> 11) & 0x1f) + 1)

#define GICD_TYPER_IRQS(typer)		((((typer) & 0x1f) + 1) * 32)



#define GICD_IROUTER_SPI_MODE_ONE	(0U << 31)