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Commit 12920591 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add updated ib_execute function for evergreen 



Adds new packet to disable DX9 constant emulation.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 63a50780

drivers/gpu/drm/radeon/evergreen.c

+13 −0
Original line number Diff line number Diff line
@@ -1185,6 +1185,18 @@ static void evergreen_mc_program(struct radeon_device *rdev) 
/*

 * CP.

 */

void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)

{

	/* set to DX10/11 mode */

	radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));

	radeon_ring_write(rdev, 1);

	/* FIXME: implement */

	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

	radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);

	radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);

	radeon_ring_write(rdev, ib->length_dw);

}





static int evergreen_cp_load_microcode(struct radeon_device *rdev)

{
@@ -2075,6 +2087,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);



	WREG32(VGT_GS_VERTEX_REUSE, 16);

	WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);

	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);



	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+7 −3
Original line number Diff line number Diff line
@@ -232,7 +232,7 @@ draw_auto(struct radeon_device *rdev) 


}



/* emits 34 */

/* emits 36 */

static void

set_default_state(struct radeon_device *rdev)

{
@@ -499,6 +499,10 @@ set_default_state(struct radeon_device *rdev) 
	radeon_ring_write(rdev, 0x00000000);

	radeon_ring_write(rdev, 0x00000000);



	/* set to DX10/11 mode */

	radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));

	radeon_ring_write(rdev, 1);



	/* emit an IB pointing at default state */

	dwords = ALIGN(rdev->r600_blit.state_len, 0x10);

	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
@@ -679,7 +683,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) 
	/* calculate number of loops correctly */

	ring_size = num_loops * dwords_per_loop;

	/* set default  + shaders */

	ring_size += 50; /* shaders + def state */

	ring_size += 52; /* shaders + def state */

	ring_size += 10; /* fence emit for VB IB */

	ring_size += 5; /* done copy */

	ring_size += 10; /* fence emit for done copy */
@@ -687,7 +691,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) 
	if (r)

		return r;



	set_default_state(rdev); /* 34 */

	set_default_state(rdev); /* 36 */

	set_shaders(rdev); /* 16 */

	return 0;

}

drivers/gpu/drm/radeon/evergreend.h

+2 −0
Original line number Diff line number Diff line
@@ -240,6 +240,7 @@ 
#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)

#define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)

#define PA_SC_LINE_STIPPLE				0x28A0C

#define	PA_SU_LINE_STIPPLE_VALUE			0x8A60

#define	PA_SC_LINE_STIPPLE_STATE			0x8B10



#define	SCRATCH_REG0					0x8500
@@ -652,6 +653,7 @@ 
#define	PACKET3_DISPATCH_DIRECT				0x15

#define	PACKET3_DISPATCH_INDIRECT			0x16

#define	PACKET3_INDIRECT_BUFFER_END			0x17

#define	PACKET3_MODE_CONTROL				0x18

#define	PACKET3_SET_PREDICATION				0x20

#define	PACKET3_REG_RMW					0x21

#define	PACKET3_COND_EXEC				0x22

drivers/gpu/drm/radeon/radeon_asic.c

+3 −3
Original line number Diff line number Diff line
@@ -759,7 +759,7 @@ static struct radeon_asic evergreen_asic = { 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.ring_test = &r600_ring_test,

	.ring_ib_execute = &r600_ring_ib_execute,

	.ring_ib_execute = &evergreen_ring_ib_execute,

	.irq_set = &evergreen_irq_set,

	.irq_process = &evergreen_irq_process,

	.get_vblank_counter = &evergreen_get_vblank_counter,
@@ -805,7 +805,7 @@ static struct radeon_asic sumo_asic = { 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.ring_test = &r600_ring_test,

	.ring_ib_execute = &r600_ring_ib_execute,

	.ring_ib_execute = &evergreen_ring_ib_execute,

	.irq_set = &evergreen_irq_set,

	.irq_process = &evergreen_irq_process,

	.get_vblank_counter = &evergreen_get_vblank_counter,
@@ -848,7 +848,7 @@ static struct radeon_asic btc_asic = { 
	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.ring_test = &r600_ring_test,

	.ring_ib_execute = &r600_ring_ib_execute,

	.ring_ib_execute = &evergreen_ring_ib_execute,

	.irq_set = &evergreen_irq_set,

	.irq_process = &evergreen_irq_process,

	.get_vblank_counter = &evergreen_get_vblank_counter,

drivers/gpu/drm/radeon/radeon_asic.h

+1 −0
Original line number Diff line number Diff line
@@ -355,6 +355,7 @@ int evergreen_resume(struct radeon_device *rdev); 
bool evergreen_gpu_is_lockup(struct radeon_device *rdev);

int evergreen_asic_reset(struct radeon_device *rdev);

void evergreen_bandwidth_update(struct radeon_device *rdev);

void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);

int evergreen_copy_blit(struct radeon_device *rdev,

			uint64_t src_offset, uint64_t dst_offset,

			unsigned num_pages, struct radeon_fence *fence);