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Commit 128a9b1d authored by Lucas Stach's avatar Lucas Stach
Browse files

drm/etnaviv: handle MMU exception in IRQ handler 



Bit 30 of the interrupt status signals an MMU exception. Handle this
condition properly and dump some useful registers.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
parent 2e145a22

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

+15 −0
Original line number Original line Diff line number Diff line
@@ -1363,6 +1363,21 @@ static irqreturn_t irq_handler(int irq, void *data) 
			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;

			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;

		}

		}





		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {

			int i;



			dev_err_ratelimited(gpu->dev,

				"MMU fault status 0x%08x\n",

				gpu_read(gpu, VIVS_MMUv2_STATUS));

			for (i = 0; i < 4; i++) {

				dev_err_ratelimited(gpu->dev,

					"MMU %d fault addr 0x%08x\n",

					i, gpu_read(gpu,

					VIVS_MMUv2_EXCEPTION_ADDR(i)));

			}

			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;

		}



		while ((event = ffs(intr)) != 0) {

		while ((event = ffs(intr)) != 0) {

			struct fence *fence;

			struct fence *fence;

drivers/gpu/drm/etnaviv/state_hi.xml.h

+5 −4
Original line number Original line Diff line number Diff line
@@ -8,10 +8,10 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone git://0x04.net/rules-ng-ng

git clone git://0x04.net/rules-ng-ng





The rules-ng-ng source files this header was generated from are:

The rules-ng-ng source files this header was generated from are:

- state_hi.xml (  24309 bytes, from 2015-12-12 09:02:53)

- state_hi.xml (  25620 bytes, from 2016-08-19 22:07:37)

- common.xml   (  18437 bytes, from 2015-12-12 09:02:53)

- common.xml   (  20583 bytes, from 2016-06-07 05:22:38)





Copyright (C) 2015

Copyright (C) 2016

*/

*/
@@ -78,9 +78,10 @@ Copyright (C) 2015 
#define VIVS_HI_AXI_STATUS_DET_RD_ERR				0x00000200

#define VIVS_HI_AXI_STATUS_DET_RD_ERR				0x00000200





#define VIVS_HI_INTR_ACKNOWLEDGE				0x00000010

#define VIVS_HI_INTR_ACKNOWLEDGE				0x00000010

#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK			0x7fffffff

#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK			0x3fffffff

#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT		0

#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT		0

#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x)			(((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)

#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x)			(((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)

#define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION			0x40000000

#define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR			0x80000000

#define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR			0x80000000





#define VIVS_HI_INTR_ENBL					0x00000014

#define VIVS_HI_INTR_ENBL					0x00000014