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Commit 0fcdb61e authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms/evergreen: add gart support 



Gart setup is more or less like r7xx.  Copy
rv770d.h to evergreend.h and fix up changes.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 49f65982

drivers/gpu/drm/radeon/evergreen.c

+39 −19
Original line number Original line Diff line number Diff line
@@ -27,7 +27,7 @@ 
#include "radeon.h"

#include "radeon.h"

#include "radeon_asic.h"

#include "radeon_asic.h"

#include "radeon_drm.h"

#include "radeon_drm.h"

#include "rv770d.h"

#include "evergreend.h"

#include "atom.h"

#include "atom.h"

#include "avivod.h"

#include "avivod.h"

#include "evergreen_reg.h"

#include "evergreen_reg.h"
@@ -82,10 +82,31 @@ static int evergreen_mc_wait_for_idle(struct radeon_device *rdev) 
/*

/*

 * GART

 * GART

 */

 */

void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)

{

	unsigned i;

	u32 tmp;



	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));

	for (i = 0; i < rdev->usec_timeout; i++) {

		/* read MC_STATUS */

		tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);

		tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;

		if (tmp == 2) {

			printk(KERN_WARNING "[drm] r600 flush TLB failed\n");

			return;

		}

		if (tmp) {

			return;

		}

		udelay(1);

	}

}



int evergreen_pcie_gart_enable(struct radeon_device *rdev)

int evergreen_pcie_gart_enable(struct radeon_device *rdev)

{

{

	u32 tmp;

	u32 tmp;

	int r, i;

	int r;





	if (rdev->gart.table.vram.robj == NULL) {

	if (rdev->gart.table.vram.robj == NULL) {

		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");

		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
@@ -120,10 +141,9 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev) 
				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);

	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

			(u32)(rdev->dummy_page.addr >> 12));

			(u32)(rdev->dummy_page.addr >> 12));

	for (i = 1; i < 7; i++)

	WREG32(VM_CONTEXT1_CNTL, 0);

		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);





	r600_pcie_gart_tlb_flush(rdev);

	evergreen_pcie_gart_tlb_flush(rdev);

	rdev->gart.ready = true;

	rdev->gart.ready = true;

	return 0;

	return 0;

}

}
@@ -131,11 +151,11 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev) 
void evergreen_pcie_gart_disable(struct radeon_device *rdev)

void evergreen_pcie_gart_disable(struct radeon_device *rdev)

{

{

	u32 tmp;

	u32 tmp;

	int i, r;

	int r;





	/* Disable all tables */

	/* Disable all tables */

	for (i = 0; i < 7; i++)

	WREG32(VM_CONTEXT0_CNTL, 0);

		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

	WREG32(VM_CONTEXT1_CNTL, 0);





	/* Setup L2 cache */

	/* Setup L2 cache */

	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |

	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
@@ -172,7 +192,6 @@ void evergreen_pcie_gart_fini(struct radeon_device *rdev) 
void evergreen_agp_enable(struct radeon_device *rdev)

void evergreen_agp_enable(struct radeon_device *rdev)

{

{

	u32 tmp;

	u32 tmp;

	int i;





	/* Setup L2 cache */

	/* Setup L2 cache */

	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
@@ -192,8 +211,8 @@ void evergreen_agp_enable(struct radeon_device *rdev) 
	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

	for (i = 0; i < 7; i++)

	WREG32(VM_CONTEXT0_CNTL, 0);

		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

	WREG32(VM_CONTEXT1_CNTL, 0);

}

}





static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)

static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -500,9 +519,9 @@ int evergreen_asic_reset(struct radeon_device *rdev) 




static int evergreen_startup(struct radeon_device *rdev)

static int evergreen_startup(struct radeon_device *rdev)

{

{

#if 0

	int r;

	int r;





#if 0

	if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {

	if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {

		r = r600_init_microcode(rdev);

		r = r600_init_microcode(rdev);

		if (r) {

		if (r) {
@@ -512,15 +531,13 @@ static int evergreen_startup(struct radeon_device *rdev) 
	}

	}

#endif

#endif

	evergreen_mc_program(rdev);

	evergreen_mc_program(rdev);

#if 0

	if (rdev->flags & RADEON_IS_AGP) {

	if (rdev->flags & RADEON_IS_AGP) {

		evergreem_agp_enable(rdev);

		evergreen_agp_enable(rdev);

	} else {

	} else {

		r = evergreen_pcie_gart_enable(rdev);

		r = evergreen_pcie_gart_enable(rdev);

		if (r)

		if (r)

			return r;

			return r;

	}

	}

#endif

	evergreen_gpu_init(rdev);

	evergreen_gpu_init(rdev);

#if 0

#if 0

	if (!rdev->r600_blit.shader_obj) {

	if (!rdev->r600_blit.shader_obj) {
@@ -607,7 +624,10 @@ int evergreen_suspend(struct radeon_device *rdev) 
	r700_cp_stop(rdev);

	r700_cp_stop(rdev);

	rdev->cp.ready = false;

	rdev->cp.ready = false;

	r600_wb_disable(rdev);

	r600_wb_disable(rdev);

#endif



	evergreen_pcie_gart_disable(rdev);

	evergreen_pcie_gart_disable(rdev);

#if 0

	/* unpin shaders bo */

	/* unpin shaders bo */

	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);

	r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);

	if (likely(r == 0)) {

	if (likely(r == 0)) {
@@ -717,18 +737,18 @@ int evergreen_init(struct radeon_device *rdev) 




	rdev->ih.ring_obj = NULL;

	rdev->ih.ring_obj = NULL;

	r600_ih_ring_init(rdev, 64 * 1024);

	r600_ih_ring_init(rdev, 64 * 1024);



#endif

	r = r600_pcie_gart_init(rdev);

	r = r600_pcie_gart_init(rdev);

	if (r)

	if (r)

		return r;

		return r;

#endif



	rdev->accel_working = false;

	rdev->accel_working = false;

	r = evergreen_startup(rdev);

	r = evergreen_startup(rdev);

	if (r) {

	if (r) {

		evergreen_suspend(rdev);

		evergreen_suspend(rdev);

		/*r600_wb_fini(rdev);*/

		/*r600_wb_fini(rdev);*/

		/*radeon_ring_fini(rdev);*/

		/*radeon_ring_fini(rdev);*/

		/*evergreen_pcie_gart_fini(rdev);*/

		evergreen_pcie_gart_fini(rdev);

		rdev->accel_working = false;

		rdev->accel_working = false;

	}

	}

	if (rdev->accel_working) {

	if (rdev->accel_working) {
@@ -756,8 +776,8 @@ void evergreen_fini(struct radeon_device *rdev) 
	radeon_irq_kms_fini(rdev);

	radeon_irq_kms_fini(rdev);

	radeon_ring_fini(rdev);

	radeon_ring_fini(rdev);

	r600_wb_fini(rdev);

	r600_wb_fini(rdev);

	evergreen_pcie_gart_fini(rdev);

#endif

#endif

	evergreen_pcie_gart_fini(rdev);

	radeon_gem_fini(rdev);

	radeon_gem_fini(rdev);

	radeon_fence_driver_fini(rdev);

	radeon_fence_driver_fini(rdev);

	radeon_clocks_fini(rdev);

	radeon_clocks_fini(rdev);

drivers/gpu/drm/radeon/evergreend.h

0 → 100644
+270 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright 2010 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Alex Deucher

 */

#ifndef EVERGREEND_H

#define EVERGREEND_H



/* Registers */



#define	CC_GC_SHADER_PIPE_CONFIG			0x8950

#define	CC_RB_BACKEND_DISABLE				0x98F4

#define		BACKEND_DISABLE(x)				((x) << 16)

#define	CC_SYS_RB_BACKEND_DISABLE			0x3F88



#define	CGTS_SYS_TCC_DISABLE				0x3F90

#define	CGTS_TCC_DISABLE				0x9148

#define	CGTS_USER_SYS_TCC_DISABLE			0x3F94

#define	CGTS_USER_TCC_DISABLE				0x914C



#define	CONFIG_MEMSIZE					0x5428



#define	CP_ME_CNTL					0x86D8

#define		CP_ME_HALT					(1<<28)

#define		CP_PFP_HALT					(1<<26)

#define	CP_ME_RAM_DATA					0xC160

#define	CP_ME_RAM_RADDR					0xC158

#define	CP_ME_RAM_WADDR					0xC15C

#define CP_MEQ_THRESHOLDS				0x8764

#define		STQ_SPLIT(x)					((x) << 0)

#define	CP_PERFMON_CNTL					0x87FC

#define	CP_PFP_UCODE_ADDR				0xC150

#define	CP_PFP_UCODE_DATA				0xC154

#define	CP_QUEUE_THRESHOLDS				0x8760

#define		ROQ_IB1_START(x)				((x) << 0)

#define		ROQ_IB2_START(x)				((x) << 8)

#define	CP_RB_CNTL					0xC104

#define		RB_BUFSZ(x)					((x)<<0)

#define		RB_BLKSZ(x)					((x)<<8)

#define		RB_NO_UPDATE					(1<<27)

#define		RB_RPTR_WR_ENA					(1<<31)

#define		BUF_SWAP_32BIT					(2 << 16)

#define	CP_RB_RPTR					0x8700

#define	CP_RB_RPTR_ADDR					0xC10C

#define	CP_RB_RPTR_ADDR_HI				0xC110

#define	CP_RB_RPTR_WR					0xC108

#define	CP_RB_WPTR					0xC114

#define	CP_RB_WPTR_ADDR					0xC118

#define	CP_RB_WPTR_ADDR_HI				0xC11C

#define	CP_RB_WPTR_DELAY				0x8704

#define	CP_SEM_WAIT_TIMER				0x85BC





#define	GC_USER_SHADER_PIPE_CONFIG			0x8954

#define		INACTIVE_QD_PIPES(x)				((x) << 8)

#define		INACTIVE_QD_PIPES_MASK				0x0000FF00

#define		INACTIVE_SIMDS(x)				((x) << 16)

#define		INACTIVE_SIMDS_MASK				0x00FF0000



#define	GRBM_CNTL					0x8000

#define		GRBM_READ_TIMEOUT(x)				((x) << 0)

#define	GRBM_SOFT_RESET					0x8020

#define		SOFT_RESET_CP					(1<<0)

#define	GRBM_STATUS					0x8010

#define		CMDFIFO_AVAIL_MASK				0x0000000F

#define		GUI_ACTIVE					(1<<31)



#define	HDP_HOST_PATH_CNTL				0x2C00

#define	HDP_NONSURFACE_BASE				0x2C04

#define	HDP_NONSURFACE_INFO				0x2C08

#define	HDP_NONSURFACE_SIZE				0x2C0C

#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0

#define	HDP_TILING_CONFIG				0x2F3C



#define MC_SHARED_CHMAP						0x2004

#define		NOOFCHAN_SHIFT					12

#define		NOOFCHAN_MASK					0x00003000



#define	MC_ARB_RAMCFG					0x2760

#define		NOOFBANK_SHIFT					0

#define		NOOFBANK_MASK					0x00000003

#define		NOOFRANK_SHIFT					2

#define		NOOFRANK_MASK					0x00000004

#define		NOOFROWS_SHIFT					3

#define		NOOFROWS_MASK					0x00000038

#define		NOOFCOLS_SHIFT					6

#define		NOOFCOLS_MASK					0x000000C0

#define		CHANSIZE_SHIFT					8

#define		CHANSIZE_MASK					0x00000100

#define		BURSTLENGTH_SHIFT				9

#define		BURSTLENGTH_MASK				0x00000200

#define		CHANSIZE_OVERRIDE				(1 << 11)

#define	MC_VM_AGP_TOP					0x2028

#define	MC_VM_AGP_BOT					0x202C

#define	MC_VM_AGP_BASE					0x2030

#define	MC_VM_FB_LOCATION				0x2024

#define	MC_VM_MB_L1_TLB0_CNTL				0x2234

#define	MC_VM_MB_L1_TLB1_CNTL				0x2238

#define	MC_VM_MB_L1_TLB2_CNTL				0x223C

#define	MC_VM_MB_L1_TLB3_CNTL				0x2240

#define		ENABLE_L1_TLB					(1 << 0)

#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)

#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)

#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)

#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)

#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)

#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)

#define		EFFECTIVE_L1_TLB_SIZE(x)			((x)<<15)

#define		EFFECTIVE_L1_QUEUE_SIZE(x)			((x)<<18)

#define	MC_VM_MD_L1_TLB0_CNTL				0x2654

#define	MC_VM_MD_L1_TLB1_CNTL				0x2658

#define	MC_VM_MD_L1_TLB2_CNTL				0x265C

#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C

#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038

#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034



#define	PA_CL_ENHANCE					0x8A14

#define		CLIP_VTX_REORDER_ENA				(1 << 0)

#define		NUM_CLIP_SEQ(x)					((x) << 1)

#define PA_SC_AA_CONFIG					0x28C04

#define PA_SC_CLIPRECT_RULE				0x2820C

#define	PA_SC_EDGERULE					0x28230

#define	PA_SC_FIFO_SIZE					0x8BCC

#define		SC_PRIM_FIFO_SIZE(x)				((x) << 0)

#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 12)

#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24

#define		FORCE_EOV_MAX_CLK_CNT(x)			((x)<<0)

#define		FORCE_EOV_MAX_REZ_CNT(x)			((x)<<16)

#define PA_SC_LINE_STIPPLE				0x28A0C

#define	PA_SC_LINE_STIPPLE_STATE			0x8B10



#define	SCRATCH_REG0					0x8500

#define	SCRATCH_REG1					0x8504

#define	SCRATCH_REG2					0x8508

#define	SCRATCH_REG3					0x850C

#define	SCRATCH_REG4					0x8510

#define	SCRATCH_REG5					0x8514

#define	SCRATCH_REG6					0x8518

#define	SCRATCH_REG7					0x851C

#define	SCRATCH_UMSK					0x8540

#define	SCRATCH_ADDR					0x8544



#define	SMX_DC_CTL0					0xA020

#define		USE_HASH_FUNCTION				(1 << 0)

#define		CACHE_DEPTH(x)					((x) << 1)

#define		FLUSH_ALL_ON_EVENT				(1 << 10)

#define		STALL_ON_EVENT					(1 << 11)

#define	SMX_EVENT_CTL					0xA02C

#define		ES_FLUSH_CTL(x)					((x) << 0)

#define		GS_FLUSH_CTL(x)					((x) << 3)

#define		ACK_FLUSH_CTL(x)				((x) << 6)

#define		SYNC_FLUSH_CTL					(1 << 8)



#define	SPI_CONFIG_CNTL					0x9100

#define		GPR_WRITE_PRIORITY(x)				((x) << 0)

#define	SPI_CONFIG_CNTL_1				0x913C

#define		VTX_DONE_DELAY(x)				((x) << 0)

#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)

#define	SPI_INPUT_Z					0x286D8

#define	SPI_PS_IN_CONTROL_0				0x286CC

#define		NUM_INTERP(x)					((x)<<0)

#define		POSITION_ENA					(1<<8)

#define		POSITION_CENTROID				(1<<9)

#define		POSITION_ADDR(x)				((x)<<10)

#define		PARAM_GEN(x)					((x)<<15)

#define		PARAM_GEN_ADDR(x)				((x)<<19)

#define		BARYC_SAMPLE_CNTL(x)				((x)<<26)

#define		PERSP_GRADIENT_ENA				(1<<28)

#define		LINEAR_GRADIENT_ENA				(1<<29)

#define		POSITION_SAMPLE					(1<<30)

#define		BARYC_AT_SAMPLE_ENA				(1<<31)



#define	SQ_CONFIG					0x8C00

#define		VC_ENABLE					(1 << 0)

#define		EXPORT_SRC_C					(1 << 1)

#define	SQ_GPR_RESOURCE_MGMT_1				0x8C04

#define		NUM_PS_GPRS(x)					((x) << 0)

#define		NUM_VS_GPRS(x)					((x) << 16)

#define		NUM_CLAUSE_TEMP_GPRS(x)				((x) << 28)

#define	SQ_GPR_RESOURCE_MGMT_2				0x8C08

#define		NUM_GS_GPRS(x)					((x) << 0)

#define		NUM_ES_GPRS(x)					((x) << 16)

#define	SQ_MS_FIFO_SIZES				0x8CF0

#define		CACHE_FIFO_SIZE(x)				((x) << 0)

#define		FETCH_FIFO_HIWATER(x)				((x) << 8)

#define		DONE_FIFO_HIWATER(x)				((x) << 16)

#define		ALU_UPDATE_FIFO_HIWATER(x)			((x) << 24)



#define	SX_DEBUG_1					0x9058

#define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)

#define	SX_EXPORT_BUFFER_SIZES				0x900C

#define		COLOR_BUFFER_SIZE(x)				((x) << 0)

#define		POSITION_BUFFER_SIZE(x)				((x) << 8)

#define		SMX_BUFFER_SIZE(x)				((x) << 16)

#define	SX_MISC						0x28350



#define	TA_CNTL_AUX					0x9508

#define		DISABLE_CUBE_WRAP				(1 << 0)

#define		DISABLE_CUBE_ANISO				(1 << 1)

#define		SYNC_GRADIENT					(1 << 24)

#define		SYNC_WALKER					(1 << 25)

#define		SYNC_ALIGNER					(1 << 26)



#define	VGT_CACHE_INVALIDATION				0x88C4

#define		CACHE_INVALIDATION(x)				((x)<<0)

#define			VC_ONLY						0

#define			TC_ONLY						1

#define			VC_AND_TC					2

#define		AUTO_INVLD_EN(x)				((x) << 6)

#define			NO_AUTO						0

#define			ES_AUTO						1

#define			GS_AUTO						2

#define			ES_AND_GS_AUTO					3

#define	VGT_GS_VERTEX_REUSE				0x88D4

#define	VGT_NUM_INSTANCES				0x8974

#define	VGT_OUT_DEALLOC_CNTL				0x28C5C

#define		DEALLOC_DIST_MASK				0x0000007F

#define	VGT_VERTEX_REUSE_BLOCK_CNTL			0x28C58

#define		VTX_REUSE_DEPTH_MASK				0x000000FF



#define VM_CONTEXT0_CNTL				0x1410

#define		ENABLE_CONTEXT					(1 << 0)

#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)

#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)

#define VM_CONTEXT1_CNTL				0x1414

#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153C

#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C

#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155C

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518

#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470

#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)

#define		RESPONSE_TYPE_MASK				0x000000F0

#define		RESPONSE_TYPE_SHIFT				4

#define VM_L2_CNTL					0x1400

#define		ENABLE_L2_CACHE					(1 << 0)

#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)

#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)

#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 14)

#define VM_L2_CNTL2					0x1404

#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)

#define		INVALIDATE_L2_CACHE				(1 << 1)

#define VM_L2_CNTL3					0x1408

#define		BANK_SELECT(x)					((x) << 0)

#define		CACHE_UPDATE_MODE(x)				((x) << 6)

#define	VM_L2_STATUS					0x140C

#define		L2_BUSY						(1 << 0)



#define	WAIT_UNTIL					0x8040



#define	SRBM_STATUS				        0x0E50



#endif

drivers/gpu/drm/radeon/radeon_asic.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -639,7 +639,7 @@ static struct radeon_asic evergreen_asic = { 
	.gpu_is_lockup = &evergreen_gpu_is_lockup,

	.gpu_is_lockup = &evergreen_gpu_is_lockup,

	.asic_reset = &evergreen_asic_reset,

	.asic_reset = &evergreen_asic_reset,

	.vga_set_state = &r600_vga_set_state,

	.vga_set_state = &r600_vga_set_state,

	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,

	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.gart_set_page = &rs600_gart_set_page,

	.ring_test = NULL,

	.ring_test = NULL,

	.ring_ib_execute = NULL,

	.ring_ib_execute = NULL,

drivers/gpu/drm/radeon/radeon_asic.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -281,6 +281,7 @@ int rv770_resume(struct radeon_device *rdev); 
/*

/*

 * evergreen

 * evergreen

 */

 */

void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);

int evergreen_init(struct radeon_device *rdev);

int evergreen_init(struct radeon_device *rdev);

void evergreen_fini(struct radeon_device *rdev);

void evergreen_fini(struct radeon_device *rdev);

int evergreen_suspend(struct radeon_device *rdev);

int evergreen_suspend(struct radeon_device *rdev);