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Commit 0f548098 authored by Gevorg Sahakyan's avatar Gevorg Sahakyan Committed by Felipe Balbi
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usb: dwc2: Move dwc2_readl/writel functions after hsotg structure 



Moved dwc2_readl/writel functions after hsotg declaration for
adding hsotg structure to dwc2_readl/writel function prototypes.

Acked-by: default avatarMinas Harutyunyan <hminas@synopsys.com>
Signed-off-by: default avatarGevorg Sahakyan <sahakyan@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent 8c45fbcd

drivers/usb/dwc2/core.h

+54 −54
Original line number Diff line number Diff line
@@ -65,60 +65,6 @@ 
	DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt),		\

				dev_name(hsotg->dev), ##__VA_ARGS__)



#ifdef CONFIG_MIPS

/*

 * There are some MIPS machines that can run in either big-endian

 * or little-endian mode and that use the dwc2 register without

 * a byteswap in both ways.

 * Unlike other architectures, MIPS apparently does not require a

 * barrier before the __raw_writel() to synchronize with DMA but does

 * require the barrier after the __raw_writel() to serialize a set of

 * writes. This set of operations was added specifically for MIPS and

 * should only be used there.

 */

static inline u32 dwc2_readl(const void __iomem *addr)

{

	u32 value = __raw_readl(addr);



	/* In order to preserve endianness __raw_* operation is used. Therefore

	 * a barrier is needed to ensure IO access is not re-ordered across

	 * reads or writes

	 */

	mb();

	return value;

}



static inline void dwc2_writel(u32 value, void __iomem *addr)

{

	__raw_writel(value, addr);



	/*

	 * In order to preserve endianness __raw_* operation is used. Therefore

	 * a barrier is needed to ensure IO access is not re-ordered across

	 * reads or writes

	 */

	mb();

#ifdef DWC2_LOG_WRITES

	pr_info("INFO:: wrote %08x to %p\n", value, addr);

#endif

}

#else

/* Normal architectures just use readl/write */

static inline u32 dwc2_readl(const void __iomem *addr)

{

	return readl(addr);

}



static inline void dwc2_writel(u32 value, void __iomem *addr)

{

	writel(value, addr);



#ifdef DWC2_LOG_WRITES

	pr_info("info:: wrote %08x to %p\n", value, addr);

#endif

}

#endif



/* Maximum number of Endpoints/HostChannels */

#define MAX_EPS_CHANNELS	16
@@ -1215,6 +1161,60 @@ struct dwc2_hsotg { 
#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */

};



#ifdef CONFIG_MIPS

/*

 * There are some MIPS machines that can run in either big-endian

 * or little-endian mode and that use the dwc2 register without

 * a byteswap in both ways.

 * Unlike other architectures, MIPS apparently does not require a

 * barrier before the __raw_writel() to synchronize with DMA but does

 * require the barrier after the __raw_writel() to serialize a set of

 * writes. This set of operations was added specifically for MIPS and

 * should only be used there.

 */

static inline u32 dwc2_readl(const void __iomem *addr)

{

	u32 value = __raw_readl(addr);



	/* In order to preserve endianness __raw_* operation is used. Therefore

	 * a barrier is needed to ensure IO access is not re-ordered across

	 * reads or writes

	 */

	mb();

	return value;

}



static inline void dwc2_writel(u32 value, void __iomem *addr)

{

	__raw_writel(value, addr);



	/*

	 * In order to preserve endianness __raw_* operation is used. Therefore

	 * a barrier is needed to ensure IO access is not re-ordered across

	 * reads or writes

	 */

	mb();

#ifdef DWC2_LOG_WRITES

	pr_info("INFO:: wrote %08x to %p\n", value, addr);

#endif

}

#else

/* Normal architectures just use readl/write */

static inline u32 dwc2_readl(const void __iomem *addr)

{

	return readl(addr);

}



static inline void dwc2_writel(u32 value, void __iomem *addr)

{

	writel(value, addr);



#ifdef DWC2_LOG_WRITES

	pr_info("info:: wrote %08x to %p\n", value, addr);

#endif

}

#endif



/* Reasons for halting a host channel */

enum dwc2_halt_status {

	DWC2_HC_XFER_NO_HALT_STATUS,