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Commit 0f4d5641 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mvebu-dt-3.15-5' of git://git.infradead.org/linux-mvebu into next/dt 

Merge "mvebu dt changes for v3.15 (incremental #5)" from Jason Cooper:

 - mvebu

    - 38x
       - add 2GHz fixed clock, core divider clock, and nand controller

    - 385
       - add nand controller and partitions to 385-DB board

* tag 'mvebu-dt-3.15-5' of git://git.infradead.org/linux-mvebu

:
  ARM: mvebu: Enable NAND controller in Armada 385-DB
  ARM: mvebu: Add support for NAND controller in Armada 38x SoC
  ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs
  ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 64d865f4 4de29e63

arch/arm/boot/dts/armada-385-db.dts

+21 −0
Original line number Diff line number Diff line
@@ -80,6 +80,27 @@ 
					reg = <1>;

				};

			};



			flash@d0000 {

				status = "okay";

				num-cs = <1>;

				marvell,nand-keep-config;

				marvell,nand-enable-arbiter;

				nand-on-flash-bbt;



				partition@0 {

					label = "U-Boot";

					reg = <0 0x800000>;

				};

				partition@800000 {

					label = "Linux";

					reg = <0x800000 0x800000>;

				};

				partition@1000000 {

					label = "Filesystem";

					reg = <0x1000000 0x3f000000>;

				};

			};

		};



		pcie-controller {

arch/arm/boot/dts/armada-38x.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -337,10 +337,35 @@ 
				compatible = "marvell,orion-mdio";

				reg = <0x72004 0x4>;

			};



			coredivclk: clock@e4250 {

				compatible = "marvell,armada-380-corediv-clock";

				reg = <0xe4250 0xc>;

				#clock-cells = <1>;

				clocks = <&mainpll>;

				clock-output-names = "nand";

			};



			flash@d0000 {

				compatible = "marvell,armada370-nand";

				reg = <0xd0000 0x54>;

				#address-cells = <1>;

				#size-cells = <1>;

				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&coredivclk 0>;

				status = "disabled";

			};

		};

	};



	clocks {

		/* 2 GHz fixed main PLL */

		mainpll: mainpll {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <2000000000>;

		};



		/* 25 MHz reference crystal */

		refclk: oscillator {

			compatible = "fixed-clock";