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Commit 0e5f61b0 authored by Andi Kleen's avatar Andi Kleen Committed by Linus Torvalds
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[PATCH] x86_64: On Intel systems when CPU has C3 don't use TSC 



On Intel systems generally the TSC stops in C3 or deeper,
so don't use it there. Follows similar logic on i386.

This should fix problems on Meroms.

Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 260f659b

arch/x86_64/kernel/time.c

+12 −4
Original line number Original line Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <linux/acpi.h>

#include <linux/acpi.h>

#ifdef CONFIG_ACPI

#ifdef CONFIG_ACPI

#include <acpi/achware.h>	/* for PM timer frequency */

#include <acpi/achware.h>	/* for PM timer frequency */

#include <acpi/acpi_bus.h>

#endif

#endif

#include <asm/8253pit.h>

#include <asm/8253pit.h>

#include <asm/pgtable.h>

#include <asm/pgtable.h>
@@ -953,11 +954,18 @@ __cpuinit int unsynchronized_tsc(void) 
#ifdef CONFIG_SMP

#ifdef CONFIG_SMP

	if (apic_is_clustered_box())

	if (apic_is_clustered_box())

		return 1;

		return 1;

 	/* Intel systems are normally all synchronized. Exceptions

 	   are handled in the check above. */

 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)

 		return 0;

#endif

#endif

	/* Most intel systems have synchronized TSCs except for

	   multi node systems */

 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {

#ifdef CONFIG_ACPI

		/* But TSC doesn't tick in C3 so don't use it there */

		if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100)

			return 1;

#endif

 		return 0;

	}



 	/* Assume multi socket systems are not synchronized */

 	/* Assume multi socket systems are not synchronized */

 	return num_present_cpus() > 1;

 	return num_present_cpus() > 1;

}

}