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Commit 0e23b99d authored by Jesse Barnes's avatar Jesse Barnes Committed by Chris Wilson
Browse files

drm/i915: split Ironlake FDI enable function 



Easier to read, and will pair up with a disable function.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent c98e9dcf

drivers/gpu/drm/i915/intel_display.c

+45 −27
Original line number Diff line number Diff line
@@ -1848,47 +1848,21 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) 
	DRM_DEBUG_KMS("FDI train done.\n");

}



static void ironlake_crtc_enable(struct drm_crtc *crtc)

static void ironlake_fdi_enable(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	int plane = intel_crtc->plane;

	int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;

	int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;

	int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;

	int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;

	int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;

	int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;

	int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;

	int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;

	int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;

	int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;

	int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;

	int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;

	int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;

	int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;

	int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;

	int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;

	int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;

	int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;

	int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;

	int trans_dpll_sel = (pipe == 0) ? 0 : 1;

	u32 temp;

	u32 pipe_bpc;



	temp = I915_READ(pipeconf_reg);

	pipe_bpc = temp & PIPE_BPC_MASK;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

		temp = I915_READ(PCH_LVDS);

		if ((temp & LVDS_PORT_EN) == 0) {

			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);

			POSTING_READ(PCH_LVDS);

		}

	}



	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */

	temp = I915_READ(fdi_rx_reg);

	/*
@@ -1916,6 +1890,50 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
		I915_READ(fdi_tx_reg);

		udelay(100);

	}

}



static void ironlake_crtc_enable(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	int plane = intel_crtc->plane;

	int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;

	int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;

	int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;

	int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;

	int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;

	int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;

	int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;

	int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;

	int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;

	int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;

	int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;

	int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;

	int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;

	int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;

	int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;

	int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;

	int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;

	int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;

	int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;

	int trans_dpll_sel = (pipe == 0) ? 0 : 1;

	u32 temp;

	u32 pipe_bpc;



	temp = I915_READ(pipeconf_reg);

	pipe_bpc = temp & PIPE_BPC_MASK;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

		temp = I915_READ(PCH_LVDS);

		if ((temp & LVDS_PORT_EN) == 0) {

			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);

			POSTING_READ(PCH_LVDS);

		}

	}



	ironlake_fdi_enable(crtc);



	/* Enable panel fitting for LVDS */

	if (dev_priv->pch_pf_size &&