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Commit 0d6fc92a authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson
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drm/i915: Separate RPS and RC6 handling for VLV 



This patch separates enable/disable of RC6 and RPS for VLV.

v2: Removed unnecessary comments about forcewakes while enabling
RC6/RPS. Added changes to output turbo control status for VLV in
i915_frequency_info.

Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarRadoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-5-git-send-email-sagar.a.kamble@intel.com


Acked-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-4-chris@chris-wilson.co.uk
parent 3a85392c

drivers/gpu/drm/i915/i915_debugfs.c

+12 −12
Original line number Diff line number Diff line
@@ -1095,9 +1095,19 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		seq_printf(m, "Current P-state: %d\n",

			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		u32 freq_sts;

		u32 rpmodectl, freq_sts;



		mutex_lock(&dev_priv->rps.hw_lock);



		rpmodectl = I915_READ(GEN6_RP_CONTROL);

		seq_printf(m, "Video Turbo Mode: %s\n",

			   yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));

		seq_printf(m, "HW control enabled: %s\n",

			   yesno(rpmodectl & GEN6_RP_ENABLE));

		seq_printf(m, "SW control enabled: %s\n",

			   yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==

				  GEN6_RP_MEDIA_SW_MODE));



		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);

		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
@@ -1508,21 +1518,11 @@ static void print_rc6_res(struct seq_file *m, 
static int vlv_drpc_info(struct seq_file *m)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	u32 rpmodectl1, rcctl1, pw_status;

	u32 rcctl1, pw_status;



	pw_status = I915_READ(VLV_GTLC_PW_STATUS);

	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);

	rcctl1 = I915_READ(GEN6_RC_CONTROL);



	seq_printf(m, "Video Turbo Mode: %s\n",

		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));

	seq_printf(m, "Turbo enabled: %s\n",

		   yesno(rpmodectl1 & GEN6_RP_ENABLE));

	seq_printf(m, "HW control enabled: %s\n",

		   yesno(rpmodectl1 & GEN6_RP_ENABLE));

	seq_printf(m, "SW control enabled: %s\n",

		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==

			  GEN6_RP_MEDIA_SW_MODE));

	seq_printf(m, "RC6 Enabled: %s\n",

		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |

					GEN6_RC_CTL_EI_MODE(1))));

drivers/gpu/drm/i915/intel_pm.c

+39 −22
Original line number Diff line number Diff line
@@ -6350,9 +6350,9 @@ static void cherryview_disable_rps(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN6_RC_CONTROL, 0);

}



static void valleyview_disable_rps(struct drm_i915_private *dev_priv)

static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)

{

	/* we're doing forcewake before Disabling RC6,

	/* We're doing forcewake before Disabling RC6,

	 * This what the BIOS expects when going into suspend */

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
@@ -6361,6 +6361,11 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv) 
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}



static void valleyview_disable_rps(struct drm_i915_private *dev_priv)

{

	I915_WRITE(GEN6_RP_CONTROL, 0);

}



static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)

{

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -7283,11 +7288,11 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv) 
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}



static void valleyview_enable_rps(struct drm_i915_private *dev_priv)

static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	u32 gtfifodbg, val, rc6_mode = 0;

	u32 gtfifodbg, rc6_mode = 0;



	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -7300,28 +7305,11 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) 
		I915_WRITE(GTFIFODBG, gtfifodbg);

	}



	/* If VLV, Forcewake all wells, else re-direct to regular path */

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	/*  Disable RC states. */

	I915_WRITE(GEN6_RC_CONTROL, 0);



	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);

	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);

	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);

	I915_WRITE(GEN6_RP_UP_EI, 66000);

	I915_WRITE(GEN6_RP_DOWN_EI, 350000);



	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);



	I915_WRITE(GEN6_RP_CONTROL,

		   GEN6_RP_MEDIA_TURBO |

		   GEN6_RP_MEDIA_HW_NORMAL_MODE |

		   GEN6_RP_MEDIA_IS_GFX |

		   GEN6_RP_ENABLE |

		   GEN6_RP_UP_BUSY_AVG |

		   GEN6_RP_DOWN_IDLE_CONT);



	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);

	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);

	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
@@ -7331,7 +7319,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) 


	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);



	/* allows RC6 residency counter to work */

	/* Allows RC6 residency counter to work */

	I915_WRITE(VLV_COUNTER_CONTROL,

		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |

				      VLV_MEDIA_RC0_COUNT_EN |
@@ -7346,6 +7334,33 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) 


	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}



static void valleyview_enable_rps(struct drm_i915_private *dev_priv)

{

	u32 val;



	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));



	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);



	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);

	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);

	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);

	I915_WRITE(GEN6_RP_UP_EI, 66000);

	I915_WRITE(GEN6_RP_DOWN_EI, 350000);



	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);



	I915_WRITE(GEN6_RP_CONTROL,

		   GEN6_RP_MEDIA_TURBO |

		   GEN6_RP_MEDIA_HW_NORMAL_MODE |

		   GEN6_RP_MEDIA_IS_GFX |

		   GEN6_RP_ENABLE |

		   GEN6_RP_UP_BUSY_AVG |

		   GEN6_RP_DOWN_IDLE_CONT);



	/* Setting Fixed Bias */

	val = VLV_OVERRIDE_EN |

		  VLV_SOC_TDP_EN |
@@ -7945,6 +7960,7 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) 
	} else if (IS_CHERRYVIEW(dev_priv)) {

		cherryview_disable_rps(dev_priv);

	} else if (IS_VALLEYVIEW(dev_priv)) {

		valleyview_disable_rc6(dev_priv);

		valleyview_disable_rps(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 6) {

		gen6_disable_rc6(dev_priv);
@@ -7974,6 +7990,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) 
	if (IS_CHERRYVIEW(dev_priv)) {

		cherryview_enable_rps(dev_priv);

	} else if (IS_VALLEYVIEW(dev_priv)) {

		valleyview_enable_rc6(dev_priv);

		valleyview_enable_rps(dev_priv);

	} else if (INTEL_GEN(dev_priv) >= 9) {

		gen9_enable_rc6(dev_priv);