Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0bf059f3 authored by Oscar Mateo's avatar Oscar Mateo Committed by Mika Kuoppala
Browse files

drm/i915/icl: WaEnableFloatBlendOptimization 



Enables blend optimization for floating point RTs

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1406393558
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1527285939-20113-5-git-send-email-oscar.mateo@intel.com
parent b1f88820

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -2663,6 +2663,9 @@ enum i915_power_well_id { 
#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)

#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)



#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)

#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)



#define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)

#define   GEN6_BLITTER_LOCK_SHIFT			16

#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)

drivers/gpu/drm/i915/intel_workarounds.c

+3 −0
Original line number Diff line number Diff line
@@ -479,6 +479,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv) 
		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,

				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);



	/* WaEnableFloatBlendOptimization:icl */

	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);



	return 0;

}