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Commit 0bc5fe85 authored by Sudarsana Reddy Kalluru's avatar Sudarsana Reddy Kalluru Committed by David S. Miller
Browse files

qed*: Refactor mf_mode to consist of bits. 



`mf_mode' field indicates the multi-partitioning mode the device is
configured to. This method doesn't scale very well, adding a new MF mode
requires going over all the existing conditions, and deciding whether those
are needed for the new mode or not.
The patch defines a set of bit-fields for modes which are derived according
to the mode info shared by the MFW and all the configuration would be made
according to those. To add a new mode, there would be a single place where
we'll need to go and choose which bits apply and which don't.

Signed-off-by: default avatarSudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com>
Signed-off-by: default avatarAriel Elior <ariel.elior@cavium.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3a443bd6

drivers/net/ethernet/qlogic/qed/qed.h

+37 −4
Original line number Diff line number Diff line
@@ -439,6 +439,41 @@ struct qed_fw_data { 
	u32			init_ops_size;

};



enum qed_mf_mode_bit {

	/* Supports PF-classification based on tag */

	QED_MF_OVLAN_CLSS,



	/* Supports PF-classification based on MAC */

	QED_MF_LLH_MAC_CLSS,



	/* Supports PF-classification based on protocol type */

	QED_MF_LLH_PROTO_CLSS,



	/* Requires a default PF to be set */

	QED_MF_NEED_DEF_PF,



	/* Allow LL2 to multicast/broadcast */

	QED_MF_LL2_NON_UNICAST,



	/* Allow Cross-PF [& child VFs] Tx-switching */

	QED_MF_INTER_PF_SWITCH,



	/* Unified Fabtic Port support enabled */

	QED_MF_UFP_SPECIFIC,



	/* Disable Accelerated Receive Flow Steering (aRFS) */

	QED_MF_DISABLE_ARFS,



	/* Use vlan for steering */

	QED_MF_8021Q_TAGGING,



	/* Use stag for steering */

	QED_MF_8021AD_TAGGING,



	/* Allow DSCP to TC mapping */

	QED_MF_DSCP_TO_TC_MAP,

};



enum BAR_ID {

	BAR_ID_0,		/* used for GRC */

	BAR_ID_1		/* Used for doorbells */
@@ -669,10 +704,8 @@ struct qed_dev { 
	u8				num_funcs_in_port;



	u8				path_id;

	enum qed_mf_mode		mf_mode;

#define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)

#define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)

#define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)



	unsigned long			mf_bits;



	int				pcie_width;

	int				pcie_speed;

drivers/net/ethernet/qlogic/qed/qed_dev.c

+19 −20
Original line number Diff line number Diff line
@@ -1149,18 +1149,10 @@ static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 
		return -EINVAL;

	}



	switch (p_hwfn->cdev->mf_mode) {

	case QED_MF_DEFAULT:

	case QED_MF_NPAR:

		hw_mode |= 1 << MODE_MF_SI;

		break;

	case QED_MF_OVLAN:

	if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))

		hw_mode |= 1 << MODE_MF_SD;

		break;

	default:

		DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");

	else

		hw_mode |= 1 << MODE_MF_SI;

	}



	hw_mode |= 1 << MODE_ASIC;
@@ -1557,7 +1549,6 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 


		/* send function start command */

		rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,

				     p_hwfn->cdev->mf_mode,

				     allow_npar_tx_switch);

		if (rc) {

			DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
@@ -2651,17 +2642,25 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 


	switch (mf_mode) {

	case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:

		p_hwfn->cdev->mf_mode = QED_MF_OVLAN;

		p_hwfn->cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);

		break;

	case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:

		p_hwfn->cdev->mf_mode = QED_MF_NPAR;

		p_hwfn->cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |

					BIT(QED_MF_LLH_PROTO_CLSS) |

					BIT(QED_MF_LL2_NON_UNICAST) |

					BIT(QED_MF_INTER_PF_SWITCH);

		break;

	case NVM_CFG1_GLOB_MF_MODE_DEFAULT:

		p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;

		p_hwfn->cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |

					BIT(QED_MF_LLH_PROTO_CLSS) |

					BIT(QED_MF_LL2_NON_UNICAST);

		if (QED_IS_BB(p_hwfn->cdev))

			p_hwfn->cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);

		break;

	}

	DP_INFO(p_hwfn, "Multi function mode is %08x\n",

		p_hwfn->cdev->mf_mode);



	DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",

		p_hwfn->cdev->mf_bits);



	/* Read Multi-function information from shmem */

	addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
@@ -3462,7 +3461,7 @@ int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 
	u32 high = 0, low = 0, en;

	int i;



	if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))

	if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))

		return 0;



	qed_llh_mac_to_filter(&high, &low, p_filter);
@@ -3507,7 +3506,7 @@ void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 
	u32 high = 0, low = 0;

	int i;



	if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))

	if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))

		return;



	qed_llh_mac_to_filter(&high, &low, p_filter);
@@ -3549,7 +3548,7 @@ qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn, 
	u32 high = 0, low = 0, en;

	int i;



	if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))

	if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))

		return 0;



	switch (type) {
@@ -3647,7 +3646,7 @@ qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn, 
	u32 high = 0, low = 0;

	int i;



	if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))

	if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))

		return;



	switch (type) {

drivers/net/ethernet/qlogic/qed/qed_ll2.c

+3 −3
Original line number Diff line number Diff line
@@ -922,9 +922,9 @@ static int qed_sp_ll2_rx_queue_start(struct qed_hwfn *p_hwfn, 
	p_ramrod->queue_id = p_ll2_conn->queue_id;

	p_ramrod->main_func_queue = p_ll2_conn->main_func_queue ? 1 : 0;



	if ((IS_MF_DEFAULT(p_hwfn) || IS_MF_SI(p_hwfn)) &&

	    p_ramrod->main_func_queue && (conn_type != QED_LL2_TYPE_ROCE) &&

	    (conn_type != QED_LL2_TYPE_IWARP)) {

	if (test_bit(QED_MF_LL2_NON_UNICAST, &p_hwfn->cdev->mf_bits) &&

	    p_ramrod->main_func_queue && conn_type != QED_LL2_TYPE_ROCE &&

	    conn_type != QED_LL2_TYPE_IWARP) {

		p_ramrod->mf_si_bcast_accept_all = 1;

		p_ramrod->mf_si_mcast_accept_all = 1;

	} else {

drivers/net/ethernet/qlogic/qed/qed_main.c

+4 −2
Original line number Diff line number Diff line
@@ -264,7 +264,8 @@ int qed_fill_dev_info(struct qed_dev *cdev, 
	dev_info->pci_mem_end = cdev->pci_params.mem_end;

	dev_info->pci_irq = cdev->pci_params.irq;

	dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);

	dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);

	dev_info->is_mf_default = !test_bit(QED_MF_LLH_MAC_CLSS,

					    &cdev->mf_bits);

	dev_info->dev_type = cdev->type;

	ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
@@ -273,7 +274,8 @@ int qed_fill_dev_info(struct qed_dev *cdev, 
		dev_info->fw_minor = FW_MINOR_VERSION;

		dev_info->fw_rev = FW_REVISION_VERSION;

		dev_info->fw_eng = FW_ENGINEERING_VERSION;

		dev_info->mf_mode = cdev->mf_mode;

		dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH,

						       &cdev->mf_bits);

		dev_info->tx_switching = true;



		if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)

drivers/net/ethernet/qlogic/qed/qed_sp.h

+1 −2
Original line number Diff line number Diff line
@@ -416,7 +416,6 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn, 
 * @param p_hwfn

 * @param p_ptt

 * @param p_tunn

 * @param mode

 * @param allow_npar_tx_switch

 *

 * @return int
@@ -425,7 +424,7 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn, 
int qed_sp_pf_start(struct qed_hwfn *p_hwfn,

		    struct qed_ptt *p_ptt,

		    struct qed_tunnel_info *p_tunn,

		    enum qed_mf_mode mode, bool allow_npar_tx_switch);

		    bool allow_npar_tx_switch);



/**

 * @brief qed_sp_pf_update - PF Function Update Ramrod