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Commit 0bbb194c authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
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coresight: Extend the PIDR mask to cover relevant bits in PIDR2 



As per coresight standards, PIDR2 register has the following format :

 [2-0]	- JEP106_bits6to4
 [3]	- JEDEC, designer ID is specified by JEDEC.

However some of the drivers only use mask of 0x3 for the PIDR2 leaving
bits [3-2] unchecked, which could potentially match the component for
a different device altogether. This patch fixes the mask and the
corresponding id bits for the existing devices.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 58f2c391

drivers/hwtracing/coresight/coresight-dynamic-replicator.c

+2 −2
Original line number Diff line number Diff line
@@ -199,8 +199,8 @@ static const struct dev_pm_ops replicator_dev_pm_ops = { 


static const struct amba_id replicator_ids[] = {

	{

		.id     = 0x0003b909,

		.mask   = 0x0003ffff,

		.id     = 0x000bb909,

		.mask   = 0x000fffff,

	},

	{

		/* Coresight SoC-600 */

drivers/hwtracing/coresight/coresight-etb10.c

+2 −2
Original line number Diff line number Diff line
@@ -748,8 +748,8 @@ static const struct dev_pm_ops etb_dev_pm_ops = { 


static const struct amba_id etb_ids[] = {

	{

		.id	= 0x0003b907,

		.mask	= 0x0003ffff,

		.id	= 0x000bb907,

		.mask	= 0x000fffff,

	},

	{ 0, 0},

};

drivers/hwtracing/coresight/coresight-etm3x.c

+12 −12
Original line number Diff line number Diff line
@@ -901,33 +901,33 @@ static const struct dev_pm_ops etm_dev_pm_ops = { 


static const struct amba_id etm_ids[] = {

	{	/* ETM 3.3 */

		.id	= 0x0003b921,

		.mask	= 0x0003ffff,

		.id	= 0x000bb921,

		.mask	= 0x000fffff,

		.data	= "ETM 3.3",

	},

	{	/* ETM 3.5 - Cortex-A5 */

		.id	= 0x0003b955,

		.mask	= 0x0003ffff,

		.id	= 0x000bb955,

		.mask	= 0x000fffff,

		.data	= "ETM 3.5",

	},

	{	/* ETM 3.5 */

		.id	= 0x0003b956,

		.mask	= 0x0003ffff,

		.id	= 0x000bb956,

		.mask	= 0x000fffff,

		.data	= "ETM 3.5",

	},

	{	/* PTM 1.0 */

		.id	= 0x0003b950,

		.mask	= 0x0003ffff,

		.id	= 0x000bb950,

		.mask	= 0x000fffff,

		.data	= "PTM 1.0",

	},

	{	/* PTM 1.1 */

		.id	= 0x0003b95f,

		.mask	= 0x0003ffff,

		.id	= 0x000bb95f,

		.mask	= 0x000fffff,

		.data	= "PTM 1.1",

	},

	{	/* PTM 1.1 Qualcomm */

		.id	= 0x0003006f,

		.mask	= 0x0003ffff,

		.id	= 0x000b006f,

		.mask	= 0x000fffff,

		.data	= "PTM 1.1",

	},

	{ 0, 0},

drivers/hwtracing/coresight/coresight-funnel.c

+2 −2
Original line number Diff line number Diff line
@@ -248,8 +248,8 @@ static const struct dev_pm_ops funnel_dev_pm_ops = { 


static const struct amba_id funnel_ids[] = {

	{

		.id     = 0x0003b908,

		.mask   = 0x0003ffff,

		.id     = 0x000bb908,

		.mask   = 0x000fffff,

	},

	{

		/* Coresight SoC-600 */

drivers/hwtracing/coresight/coresight-stm.c

+4 −4
Original line number Diff line number Diff line
@@ -917,13 +917,13 @@ static const struct dev_pm_ops stm_dev_pm_ops = { 


static const struct amba_id stm_ids[] = {

	{

		.id     = 0x0003b962,

		.mask   = 0x0003ffff,

		.id     = 0x000bb962,

		.mask   = 0x000fffff,

		.data	= "STM32",

	},

	{

		.id	= 0x0003b963,

		.mask	= 0x0003ffff,

		.id	= 0x000bb963,

		.mask	= 0x000fffff,

		.data	= "STM500",

	},

	{ 0, 0},